AS4C128M8D2
128M x 8 bit DDRII Synchronous DRAM (SDRAM)
Confidential Advanced (Rev. 1.0, Jun. /2013)
Overview
Features
JEDEC Standard Compliant The DDR2 SDRAM is a high-speed CMOS Double-Data-
Rate-Two (DDR2), synchronous dynamic random - access
JEDEC standard 1.8V I/O (SSTL_18-compatible)
memory (SDRAM) containing 1024 Mbits in a 8-bit wide
Power supplies: V & V = +1.8V 0.1V
DD DDQ
data I/Os. It is internally configured as a 8-bank DRAM, 8
Operating temperature range
banks x 16Mb addresses x 8 I/Os.
- Commercial (0 ~ 85C)
The device is designed to comply with DDR2 DRAM key
- Industrial (-40 ~ 95C)
features such as posted CAS# with additive latency, Write
Fully synchronous operation
latency = Read latency -1 and On Die Termination(ODT).
Fast clock rate: 400 MHz
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks. Inputs
Differential Clock, CK & CK#
are latched at the cross point of differential clocks (CK rising
Bidirectional single/differential data strobe
and CK# falling)
8 internal banks for concurrent operation
All I/Os are synchronized with a pair of bidirectional strobes
4-bit prefetch architecture
(DQS and DQS#) in a source synchronous fashion. The
Internal pipeline architecture
address bus is used to convey row, column, and bank
Precharge & active power down
address information in RAS #, CAS# multiplexing style.
Programmable Mode & Extended Mode registers
Accesses begin with the registration of a Bank Activate
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
command, and then it is followed by a Read or Write
command. Read and write accesses to the DDR2 SDRAM are
WRITE latency = READ latency - 1 t
CK
4 or 8-bit burst oriented; accesses start at a selected
Burst lengths: 4 or 8
location and continue for a programmed number of
Burst type: Sequential / Interleave
locations in a programmed sequence.
DLL enable/disable
Operating the eight memory banks in an interleaved fashion
On-die termination (ODT)
allows random access operation to occur at a higher rate
RoHS compliant
than is possible with standard DRAMs. An auto precharge
Auto Refresh and Self Refresh
function may be enabled to provide a self-timed row
8192 refresh cycles / 64ms precharge that is initiated at the end of the burst sequence.
A sequential and gapless data rate is possible depending on
- Average refresh period
burst length, CAS latency, and speed grade of the device.
7.8s @ 0 TC +85
3.9s @ +85 TC +95
60-ball 8 x 10 x 1.2mm (max) FBGA package
- Pb and Halogen Free
Table 1. Ordering Information
Part Number Clock Frequency Data Rate Power Supply Package
AS4C128M8D2-25BCN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V FBGA
AS4C128M8D2-25BIN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V FBGA
B: indicates 60-ball 8 x 10 x 1.2mm (max) FBGA package
C: indicates commercial temperature
I: indicates industrial temperature
N: indicates Pb and Halogen Free ROHS
Table 2. Speed Grade Information
Speed Grade Clock Frequency CAS Latency
t (ns) t (ns)
RCD RP
DDR2-800 400 MHz 5 12.5 12.5
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
1 Rev. 1.0 June 2013
AS4C128M8D2
Figure 1. Ball Assignment (FBGA Top View)
1 2 3 7 8 9
VDD RDQS# VSS VSSQ DQS# VDDQ
A
DM/
DQ6 VSSQ DQS VSSQ DQ7
B
RDQS
VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ
C
DQ4 VSSQ DQ3 DQ2 VSSQ DQ5
D
VDDL VREF VSS VSSDL CK VDD
E
CKE WE# RAS# CK# ODT
F
BA2 BA0 BA1 CAS# CS#
G
A10 A1 A2 A0 VDD
H
VSS A3 A5 A6 A4
J
A7 A9 A11 A8 VSS
K
VDD A12 NC NC A13
L
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
2 Rev. 1.0 June 2013