X-On Electronics has gained recognition as a prominent supplier of AS4C128M8D2A-25BIN DRAM across the USA, India, Europe, Australia, and various other global locations. AS4C128M8D2A-25BIN DRAM are a product manufactured by Alliance Memory. We provide cost-effective solutions for DRAM, ensuring timely deliveries around the world.

AS4C128M8D2A-25BIN Alliance Memory

AS4C128M8D2A-25BIN electronic component of Alliance Memory
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Part No.AS4C128M8D2A-25BIN
Manufacturer: Alliance Memory
Category: DRAM
Description: DRAM 1G, 1.8V, 128M x 16 DDR2 I Temp
Datasheet: AS4C128M8D2A-25BIN Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
1: USD 6.699 ea
Line Total: USD 6.7 
Availability - 163
Ship by Thu. 26 Dec to Mon. 30 Dec
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
163
Ship by Thu. 26 Dec to Mon. 30 Dec
MOQ : 1
Multiples : 1
1 : USD 6.699
10 : USD 5.555
100 : USD 5.39
264 : USD 5.192
528 : USD 5.016
1056 : USD 4.983
2640 : USD 4.961
5016 : USD 4.796
10032 : USD 4.796

   
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We are delighted to provide the AS4C128M8D2A-25BIN from our DRAM category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the AS4C128M8D2A-25BIN and other electronic components in the DRAM category and beyond.

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AS4C128M8D2A Revision History 128Mx8 DDR2 AS4C128M8D2A 60ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jan. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 65 - Rev.1.0 Jan.2018AS4C128M8D2A 128M x 8 bit DDRII Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jan. /2018) Features Overview JEDEC Standard Compliant The AS4C128M8D2A is a high-speed CMOS Double- Data-Rate-Two (DDR2), synchronous dynamic random JEDEC standard 1.8V I/O (SSTL 18-compatible) access memory (SDRAM) containing 1024 Mbits in an Power supplies: V & V = +1.8V 0.1V DD DDQ 8-bit wide data I/Os. It is internally configured as an 8- Operating temperature: bank DRAM, 8 banks x 16Mb addresses x 8 I/Os. T = 0~85C (Commercial) C The device is designed to comply with DDR2 DRAM T = -40~95 C (Industrial) C key features such as posted CAS with additive Supports JEDEC clock jitter specification latency, Write latency = Read latency -1, Off-Chip Fully synchronous operation Driver (OCD) impedance adjustment and On Die Fast clock rate: 400 MHz Termination(ODT). All of the control and address inputs are synchronized Differential Clock, CK & CK with a pair of externally supplied differential clocks. Bidirectional single/differential data strobe Inputs are latched at the cross point of differential clocks 8 internal banks for concurrent operation (CK rising and CK falling). All I/Os are synchronized 4-bit prefetch architecture with a pair of bidirectional strobes (DQS and DQS ) in Internal pipeline architecture a source synchronous fashion. The address bus is used Precharge & active power down to convey row, column, and bank address information Programmable Mode & Extended Mode registers in RAS , CAS multiplexing style. Accesses begin with Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5, 6 the registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and WRITE latency = READ latency - 1 t CK write accesses to the DDR2 SDRAM are 4 or 8-bit burst Burst lengths: 4 or 8 oriented accesses start at a selected location and Burst type: Sequential / Interleave continue for a programmed number of locations in a DLL enable/disable programmed sequence. Operating the eight memory Off-Chip Driver (OCD) banks in an interleaved fashion allows random access - Impedance Adjustment operation to occur at a higher rate than is possible with - Adjustable data-output drive strength standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is On-die termination (ODT) initiated at the end of the burst sequence. A sequential RoHS compliant and gapless data rate is possible depending on burst Auto Refresh and Self Refresh length, CAS latency, and speed grade of the device. 8192 refresh cycles / 64ms - Average refresh period 7.8 s -40 C TC +85 C 3.9 s +85 C TC +95 C 60-ball 8 x 10 x 1.2mm (max) FBGA package - Pb and Halogen Free Table 1. Ordering Information Max Clock Product part No. Org Temperature Package (MHz) AS4C128M8D2A-25BCN 128M x 8 Commercial 0C to 85C 400 60-ball FBGA AS4C128M8D2A-25BIN 128M x 8 Industrial -40C to 95C 400 60-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR2-800 400MHz 5 12.5 12.5 Confidential - 2 of 65 - Rev.1.0 Jan.2018

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
ALLIANCE MEMORY, INC.
ALLIANCE SEMI
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