AS4C128M8D3LB-12BCN Alliance Memory

AS4C128M8D3LB-12BIN AS4C128M8D3LB-12BCN Revision History 1Gb DDR3L AS4C128M8D3LB 78ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jan. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 85 - Rev.1.0 Jan.2018AS4C128M8D3LB-12BIN AS4C128M8D3LB-12BCN 128M x 8 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jan /2018) Features Overview JEDEC Standard Compliant The 1Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = +1.5V 0.075V DD DDQ DRAM. Operating temperature range: The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 bank : T = 0~95 C - Commercial C devices. These synchronous devices achieve high speed : T = -40~95 C - Industrial C double-data-rate transfer rates of up to 1600 Mb/sec/pin Supports JEDEC clock jitter specification for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address Fast clock rate: 800MHz inputs are synchronized with a pair of externally supplied Differential Clock, CK & CK differential clocks. Inputs are latched at the cross point Bidirectional differential data strobe of differential clocks (CK rising and CK falling). All I/Os - DQS & DQS are synchronized with differential DQS pair in a source 8 internal banks for concurrent operation synchronous fashion. 8n-bit prefetch architecture These devices operate with a single +1.35V -0.067V / Pipelined internal architecture +0.1V power supply and are available in BGA packages. Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 8 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Max Clock (MHz) Org Product part No Package 800 78-ball FBGA 128M x 8 Commercial 0C to 95C AS4C128M8D3LB-12BCN 800 78-ball FBGA 128M x 8 Industrial -40C to 95C AS4C128M8D3LB-12BIN Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 800 MHz 11 13.75 13.75 DDR3 L-1600 Confidential - 2 of 85 - Rev.1.0 Jan.2018