AS4C256M16D3C-12BCNTR Alliance Memory

AS4C256M16D3C Revision History 4Gb AS4C256M16D3C 1.5V 96 ball FBGA Package Date Revision Rev 1.0 Initial Release Mar.2020 Alliance Memory Inc. 12815 NE 124th Street Suite D,Kirkland WA 98034 USA Alliance Memory Inc. reserves the right to change products or specification without notice CONFIDENTIAL - 1 of 87 - REV.1.0 MARCH 2020AS4C256M16D3C 256M x 16 bit DDR3 Synchronous DRAM (SDRAM) Initial Release (Rev. 1.0, Mar. /20 20) Features Overview JEDEC Standard Compliant The 4Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is Power supplies: V & V = +1.5V 0.075V DD DDQ internally configured as an eight bank DRAM. Operating temperature range: The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank : T = 0~95 C - Commercial C devices. These synchronous devices achieve high speed - Industrial : T = -40~95 C C double-data-rate transfer rates of up to 1866 Mb/sec/pin Supports JEDEC clock jitter specification for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are Fast clock rate: 800/933MHz synchronized with a pair of externally supplied differential Differential Clock, CK & CK clocks. Inputs are latched at the cross point of differential Bidirectional differential data strobe clocks (CK rising and CK falling). All I/Os are synchronized - DQS & DQS with differential DQS pair in a source synchronous fashion. 8 internal banks for concurrent operation 8n-bit prefetch architecture Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant 96-ball 7.5 x 13.5 x 1.2mm FBGA package Auto Refresh and Self Refresh - Pb and Halogen Free Table 1. Ordering Information Temperature Product part No Max Clock (MHz) Org Package AS4C256M16D3C-10BCN 96-ball FBGA 256M x 16 Commercial 0C to 95C 933 AS4C256M16D3C-10BIN Industrial -40C to 95C 256M x 16 933 96-ball FBGA AS4C256M16D3C-1 2BCN 256M x 16 96-ball FBGA Commercial 0C to 95C 800 AS4C256M16D3C-1 2BIN 256M x 16 Industrial -40C to 95C 800 96-ball FBGA Table 2. Speed Grade Information Clock Frequency Speed Grade CAS Latency t (ns) t (ns) RCD RP 13 933MHZ DDR3-1 866 13.91 13.91 800MHZ 11 DDR3-1600 13.75 13.75 CONFIDENTIAL - 2 of 87 - REV.1.0 MARCH 2020