AS4C256M16D3C-93BCN Alliance Memory

AS4C256M16D3C Revision History 4Gb AS4C256M16D3C 1.5V 96 ball FBGA Package Date Revision Rev 1.0 Initial Release Mar.2020 Rev 1.1 Add new part AS4C256M16D3C-93BCN and specs May.2020 Alliance Memory Inc. 12815 NE 124th Street Suite D,Kirkland WA 98034 USA Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 88 - REV .1.1. May 2020AS4C256M16D3C 256M x 16 bit DDR3 Synchronous DRAM (SDRAM) (Rev. 1. 1, May. /2020) Features JEDEC Standard Compliant Write Leveling ZQ Calibration Power supplies: V & V = +1.5V 0.075V DD DDQ Dynamic ODT (Rtt Nom & Rtt WR) Operating temperature range: RoHS compliant : T = 0~95 C - Commercial C 96-ball 7.5 x 13.5 x 1.2mm FBGA package - Industrial : T = -40~95 C C Auto Refresh and Self Refresh Supports JEDEC clock jitter specification - Pb and Halogen Free Fully synchronous operation Fast clock rate: 800/933/1066MHz Differential Clock, CK & CK Bidirectional differential data strobe Overview - DQS & DQS 8 internal banks for concurrent operation The 4Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is 8n-bit prefetch architecture internally configured as an eight bank DRAM. Pipelined internal architecture The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank Precharge & active power down devices. These synchronous devices achieve high Programmable Mode & Extended Mode registers speed double-data-rate transfer rates of up to 2133 Mb/ Additive Latency (AL): 0, CL-1, CL-2 sec/pin for general applications. Programmable Burst lengths: 4, 8 The chip is designed to comply with all key DDR3 DRAM Burst type: Sequential / Interleave key features and all of the control and address inputs are synchronized with a pair of externally supplied differential Output Driver Impedance Control clocks. Inputs are latched at the cross point of differential Average refresh period clocks (CK rising and CK falling). All I/Os are synchronized - 8192 cycles/64ms (7.8us at -40C T +85C) C with differential DQS pair in a source synchronous fashion. - 8192 cycles/32ms (3.9us at +85C T +95C) C Table 1. Ordering Information Temperature Product part No Max Clock (MHz) Org Package 96-ball FBGA AS4C256M16D3C-93BCN 256M x 16 1066 Commercial 0C to 95C AS4C256M16D3C-10BCN 256M x 16 96-ball FBGA 933 Commercial 0C to 95C AS4C256M16D3C-10BIN 256M x 16 933 Industrial -40C to 95C 96-ball FBGA AS4C256M16D3C-1 2BCN 256M x 16 Commercial 0C to 95C 96-ball FBGA 800 AS4C256M16D3C-1 2BIN 256M x 16 Industrial -40C to 95C 800 96-ball FBGA Table 2. Speed Grade Information Clock Frequency Speed Grade CAS Latency t (ns) t (ns) RCD RP 14 1066MHZ DDR3- 2133 13.09 13.09 13 933MHZ 13.91 DDR3-1 866 13.91 800MHZ 11 DDR3-1600 13.75 13.75 Confidential - 2 of 88 - REV .1.1. May 2020