Product Information

AS4C256M16D3L-12BCN

AS4C256M16D3L-12BCN electronic component of Alliance Memory

Datasheet
DRAM 4G 1.35V 1600Mhz 256M x 16 DDR3
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete

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Availability Price Quantity
0 - WHS 1

MOQ : 2
Multiples : 190

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AS4C256M16D3L-12BCN
Alliance Memory

2 : USD 10.8301
5 : USD 10.5328
30 : USD 10.2355
75 : USD 9.8391
N/A

Obsolete
0 - WHS 2

MOQ : 1
Multiples : 1

Stock Image

AS4C256M16D3L-12BCN
Alliance Memory

1 : USD 9.6507
10 : USD 8.8808
25 : USD 8.6902
50 : USD 8.6597
100 : USD 7.7678
250 : USD 7.7581
500 : USD 7.7581
1000 : USD 7.6539
2000 : USD 7.3644
N/A

Obsolete

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Additional Infomation About Product

4Gb DDR3L AS4C256M16D3L Revision History AS4C256M16D3L - 96-ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet April 2014 Rev 2.0 AddedBackward compatible to VDD & VDDQ = 1.5V +/- August 2014 0.075 - page 2 Added CL=5 & CL=6 to Table 18 page 31 Updated Table 12. Recommended DC Operating Conditions page 26 Confidential 1 Rev. 2.0 Aug. /2014 4Gb DDR3L -AS4C256M16D3L 256M x 16 bit DDR3L Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 2.0, Aug. /2014) Overview Features JEDEC Standard Compliant The 4Gb AS4C256M16D3L Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to Power supplies: V & V = +1.35V DD DDQ achieve high-speed operation. It is internally configured Backward compatible: V & V = 1.5V +/- 0.075V DD DDQ as an eight bank DRAM. Operating temperature: The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 - Commercial (0 ~ 95C) bank devices. These synchronous devices achieve high - Industrial (-40 ~ 95C) speed double-data-rate transfer rates of up to 1600 Supports JEDEC clock jitter specification Mb/sec/pin for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3L Fast clock rate: 800MHz DRAM key features and all of the control and address Differential Clock, CK & CK inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the Bidirectional differential data strobe cross point of differential clocks (CK rising and CK -DQS & DQS falling). All I/Os are synchronized with differential DQS 8 internal banks for concurrent operation pair in a source synchronous fashion. 8n-bit prefetch architecture These devices operate with a single 1.35V -0.067V Internal pipeline architecture /+0.1V power supply and are available in BGA Precharge & active power down packages. Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40 TC +85 3.9s +85 TC +95 Write Leveling OCD Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 9 x 13 x 1.2mm FBGA package - Pb and Halogen Free Confidential 2 Rev. 2.0 Aug. /2014

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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