AS4C256M16D3LC-12BIN Alliance Memory

AS4C256M16D3LC Revision History 4Gb AS4C256M16D3 LC 1.35V 96 ball FBGA PACKAGE Revision Details Date Rev 1.0 Initial Release Mar.2020 Alliance Memory Inc. 12815 NE 124th Street Suite D,Kirkland WA 98034 USA Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 88 - Rev.1.0 March 2020AS4C256M16D3LC 256M x 16 bit DDR3L Synchronous DRAM (SDRAM) Initial Release (Rev. 1.0, Mar. /2020) Features Overview JEDEC Standard Compliant The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V =+1.35V (1.283V to 1.45V) DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = +1.5V 0.075V DD DDQ DRAM. Operating temperature range: The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank : T = 0~95 C - Commercial C devices. These synchronous devices achieve high speed - Industrial : T = -40~95 C C double-data-rate transfer rates of up to 1866 Mb/sec/pin Supports JEDEC clock jitter specification for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address Fast clock rate: 800/933MHz inputs are synchronized with a pair of externally supplied Differential Clock, CK & CK differential clocks. Inputs are latched at the cross point Bidirectional differential data strobe of differential clocks (CK rising and CK falling). All I/Os - DQS & DQS are synchronized with differential DQS pair in a source 8 internal banks for concurrent operation synchronous fashion. 8n-bit prefetch architecture Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 96-ball 7.5 x 13.5 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Product part No Max Clock (MHz) Org Package AS4C256M16D3 LC-10BCN 96-ball FBGA 256M x 16 Commercial 0C to 95C 933 AS4C256M16D3 LC-10BIN Industrial -40C to 95C 256M x 16 933 96-ball FBGA AS4C256M16D3 LC-1 2BCN 96-ball FBGA 256M x 16 Commercial 0C to 95C 800 AS4C256M16D3 LC-1 2BIN 256M x 16 Industrial -40C to 95C 800 96-ball FBGA Table 2. Speed Grade Information Clock Frequency Speed Grade CAS Latency t (ns) t (ns) RP RCD 13 933MHZ DDR3 L-1 866 13.91 13.91 800MHZ 11 DDR3 L-1600 13.75 13.75 Confidential - 2 of 88 - Rev.1.0 March 2020