AS4C256M32MD4V-062BAN Alliance Memory

8Gb LPDDR4X SDRAM Revision History For 8Gb LPDDR4X SDRAM 200ball FBGA Package Revision Details Date Rev 1.0 Initial Release Mar 2021 Confidential Rev. 1.0 Mar. 2021 -1 63- 8Gb LPDDR4X SDRAM 1 Overview The LPDDR4X SDRAM is organized as 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. 1.1 Features The 8Gbit LPDDR4X SDRAM offers the following Bidirectional/differential data strobe per byte of key features: data (DQS, DQS ) Configuration: DMI pin support for write data masking and DBI - x32 for 2-channels per device functionality - 8 internal banks per each channel Programmable READ and WRITE latencies (RL/WL) On-Chip ECC: Programmable and on-the-fly burst lengths (BL =16, - Single-bit error correction (per 64-bits), which will 32) maximize reliability Support non target DRAM ODT control - Optional ERR output signal per channel, which Directed per-bank refresh for concurrent bank indicates ECC event occurrence operation and ease of command scheduling - ECC Register, which controls ECC function ZQ Calibration Low-voltage Core and I/O Power Supplies: Operation Temperature: - V = 1.06-1.17V, V = 0.57-0.65V, V = 1.70- DD2 DDQ DD1 Automotive A2 (T = -40C to 105C) - C 1.95V On-chip temperature sensor to control self-refresh rate LVSTL (Low Voltage Swing Terminated Logic) On-chip temperature sensor whose status can be I/O Interface read from MR4 Internal VREF and VREF Training 200-ball x32 Discrete Package Dynamic ODT: (10mm x 14.5mm) - DQ ODT: VSSQ Termination RoHS-compliant, green packaging - CA ODT: VSS Termination Selectable output drive strength (DS) Max. Clock Frequency: 1.6GHz (3.2Gbps for one channel) 16-bit Pre-fetch DDR data bus Single data rate (multiple cycles) command/address bus Table1.SpeedGradeInformation SpeedGrade Clock DataRate ReadLatency tCK(ns) Frequency (Mb/s) (RL) LPDDR4X3200 1600MHz 3200 28 0.625 *Other clock frequencies/data rates supported please refer to AC timing tables. Confidential Rev. 1.0 Mar. 2021 -2 63-