AS4C256M8D3LA-12BIN Alliance Memory

AS4C256M8D3LA-12BIN Revision History 2Gb AS4C256M8D3LA-12BIN - 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet May. 2016 Rev 1.1 add CL=5,CWL=5 and CL=6,CWL=5 in table 18 Nov. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1/83- Rev. 1.1 Nov. 2016AS4C256M8D3LA-12BIN 256M x 8 bit DDR3L Synchronous DRAM (SDRAM) Overview Features JEDEC Standard Compliant The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = 1.5V 0.075V DD DDQ DRAM. Industrial temperature: -40~95 C (TC) The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank Supports JEDEC clock jitter specification devices. These synchronous devices achieve high Fully synchronous operation speed double-data-rate transfer rates of up to 1600 Fast clock rate: 800MHz Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3L Differential Clock, CK & CK DRAM key features and all of the control and address Bidirectional differential data strobe inputs are synchronized with a pair of externally - DQS & DQS supplied differential clocks. Inputs are latched at the 8 internal banks for concurrent operation cross point of differential clocks (CK rising and CK 8n-bit prefetch architecture falling). All I/Os are synchronized with differential DQS Pipelined internal architecture pair in a source synchronous fashion. Precharge & active power down These devices operate with a single 1.35V -0.067V/ Programmable Mode & Extended Mode registers +0.1V power supply and are available in BGA packages. Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40C TC +85C 3.9s +85C TC +95C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 8 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Max Clock (MHz) Product part No Org Package Industrial -40C to 95C 800 AS4C256M8D3LA-12B IN 78-ball FBGA 256M x 8 Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3L-1600 Confidential -2/83- Rev. 1.1 Nov. 2016