AS4C256M8D3LB-12BCN Alliance Memory

AS4C256M8D3LB-12BIN AS4C256M8D3LB-12BCN Revision History 2G DDR3L AS4C256M8D3LB 78ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet May. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0 May. 2018AS4C256M8D3LB-12BIN AS4C256M8D3LB-12BCN 256M x 8 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.0, May 2018) Features Overview JEDEC Standard Compliant The 2Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is Power supplies: V & V = +1.35V (1.283V~1.45V) DD DDQ internally configured as an eight bank DRAM. Backward compatible to V & V = +1.5V 0.075V DD DDQ The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank Operating temperature: devices. These synchronous devices achieve high speed - Commercial: T = 0~95 C C double-data-rate transfer rates of up to 1600 Mb/sec/pin - Industrial : T = -40~95 C C for general applications. Supports JEDEC clock jitter specification The chip is designed to comply with all key DDR3L Fully synchronous operation DRAM key features and all of the control and address Fast clock rate: 800MHz inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point Differential Clock, CK & CK of differential clocks (CK rising and CK falling). All I/Os Bidirectional differential data strobe are synchronized with differential DQS pair in a source - DQS & DQS synchronous fashion. 8 internal banks for concurrent operation These devices operate with a single 1.35V -0.067V/ 8n-bit prefetch architecture +0.1V power supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 8 x 10.5 x 1.2mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Product part No Temperature Org Max Clock (MHz) Package 800 78-ball FBGA Commercial 0C to 95C AS4C256M8D3LB-12BCN 256M x 8 800 78-ball FBGA AS4C256M8D3LB-12BIN Industrial -40C to 95C 256M x 8 Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t t (ns) (ns) RCD RP 800 MHz 11 13.75 13.75 DDR3L-1600 Confidential - 2 of 86 - Rev.1.0 May. 2018