Product Information

AS4C2M32SA-6TINTR

AS4C2M32SA-6TINTR electronic component of Alliance Memory

Datasheet
DRAM SDRAM,64M,3.3V 166MHz,2M x 32
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 7.7722 ea
Line Total: USD 7.77

6784 - Global Stock
Ships to you between
Mon. 27 May to Wed. 29 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
964 - WHS 1


Ships to you between Mon. 27 May to Wed. 29 May

MOQ : 1
Multiples : 1

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AS4C2M32SA-6TINTR
Alliance Memory

1 : USD 5.2095
10 : USD 4.7955
100 : USD 4.2895
250 : USD 4.278
500 : USD 4.1285
1000 : USD 4.002
10000 : USD 3.772

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Additional Infomation About Product

AS4C2M32SA-6TIN AS4C2M32SA-6TCN AS4C2M32SA-7TCN Revision History 64Mb SDRAM AS4C2M32SA - 86pin TSOP II PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet September 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1/54- Rev.1.0 Sep. 2015AS4C2M32SA-6TIN AS4C2M32SA-6TCN AS4C2M32SA-7TCN Features Overview Fast access time: 5.4 /5.4 ns The 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 67,108,864bits. It is internally Fast Clock rate: 166/143 MHz configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the Fully synchronous operation positive edge of the clock signal, CLK). Each of the 512K Internal pipelined architecture x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are Four internal banks (512K x 32bit x 4bank) burst oriented accesses start at a selected location and continue for a programmed number of locations in a Programmable Mode programmed sequence. Accesses begin with the registration of a Bank Activate command which is then - CAS Latency: 2 or 3 followed by a Read or Write command. - Burst Length: 1, 2, 4, 8, or full page The SDRAM provides for programmable Read or Write - Burst Type: Sequential or Interleaved burst lengths of 1, 2, 4, 8, or full page, with a burst - Burst-Read-Single-Write termination option. An auto precharge function may be Burst stop function enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh Individual byte controlled by DQM0-3 functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can Auto Refresh and Self Refresh choose the most suitable modes to maximize its performance. These devices are well suited for Operating Temperature: applications requiring high memory bandwidth. - Commercial (0 C~+70 C) - Industrial (-40 C~+85 C) 4096 refresh cycles/64ms Single +3.3V 0.3V power supply Interface: LVTTL Package: - 86-pin 400 x 875 mil plastic TSOP II package (Pb and Halogen Free) Table 1. Ordering Information Product part No Org Temperature Max Clock (MHz) Package AS4C2M32SA-6TIN Industrial -40C to +85C 86-pin TSOP II 2M x 32 166 MHz AS4C2M32SA-6TCN Commercial 0C to +70C 2M x 32 166 MHz 86-pin TSOP II AS4C2M32SA-7TCN Commercial 0C to +70C 2M x 32 143 MHz 86-pin TSOP II Confidential -2/54- Rev.1.0 Sep. 2015

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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