AS4C32M16D1-5BAN Revision History 512M DDR1 AS4C32M16D1-5BAN 60ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet June. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 64 - Rev.1.0 Jun. 2018AS4C32M16D1-5BAN 32M x 16 bit DDR Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jun /2018) Overview Features The AS4C32M16D1-5BAN SDRAM is a high- speed CMOS double data rate synchronous DRAM Fast clock rate: 200MHz containing 512 Mbits. It is internally configured as a AEC-Q100 Compliant quad 8M x 16 DRAM with a synchronous interface (all Differential Clock CK & CK signals are registered on the positive edge of the Bi-directional DQS clock signal, CK). Data outputs occur at both rising DLL enable/disable by EMRS edges Fully synchronous operation CK of CK and . Read and write accesses to the Internal pipeline architecture SDRAM are burst oriented accesses start at a selected location and continue for a programmed Four internal banks, 8M x 16-bit for each bank number of locations in a programmed sequence. Programmable Mode and Extended Mode registers Accesses begin with the registration of a Bank - CAS Latency: 2, 2.5, 3 Activate command which is then followed by a Read - Burst length: 2, 4, 8 or Write command. - Burst Type: Sequential & Interleaved The AS4C32M16D1-5BAN provides programmable Individual byte write mask control Read or Write burst lengths of 2, 4, or 8. An auto DM Write Latency = 0 precharge function may be enabled to provide a Auto Refresh and Self Refresh self-timed row precharge that is initiated at the end of - Not support self refresh function with TA > 85 C the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, 8192 refresh cycles / 16ms AS4C32M16D1-5BAN features programmable DLL Precharge & active power down option. By having a programmable mode register Power supplies: V V = 2.5V 0.2V DD & DDQ and extended mode register, the system can Automotive Temperature: TA = -40 C~105 C choose the most suitable modes to maximize its Interface: SSTL 2 I/O Interface performance. These devices are well suited for Package: Pb free and Halogen free applications requiring high memory bandwidth result in a device particularly well suited to high - 60 Ball, 8x13x1.2 mm (max) FBGA performance main memory and graphics applications. Table 1. Ordering Information Temperature Max Clock (MHz) Product part No Org Package 200 32M x 16 Automotive - 40C to 105C 60-ball FBGA AS4C32M16D1-5BAN Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR1-400 200MHz 15 15 3 Confidential - 2 of 64 - Rev.1.0 Jun. 2018