AS4C32M16D1 Revision History AS4C32M16D1 - 60-Ball, 8x13x1.2 mm (max) TFBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet August 2014 Confidential 1 Rev. 1.0 Aug. /2014 AS4C32M16D1 32M x 16 bit DDR Synchronous DRAM (SDRAM) TFBGA option - Advanced (Rev. 1.0, Aug. /2014) Features Overview Fast clock rate: 200MHz The AS4C32M16D1 is a high-speed CMOS double data rate synchronous DRAM containing 512 Mbits. It is Differential Clock CK & CK internally configured as a quad 8M x 16 DRAM with a Bi-directional DQS synchronous interface (all signals are registered on the DLL enable/disable by EMRS positive edge of the clock signal, CK). Data outputs Fully synchronous operation occur at both rising edges of CK and . Read and CK Internal pipeline architecture write accesses to the SDRAM are burst oriented Four internal banks, 8M x 16-bit for each bank accesses start at a selected location and continue for a Programmable Mode and Extended Mode registers programmed number of locations in a programmed sequence. Accesses begin with the registration of a - CAS Latency: 2, 2.5, 3 BankActivate command which is then followed by a - Burst length: 2, 4, 8 Read or Write command. The device provides - Burst Type: Sequential & Interleaved programmable Read or Write burst lengths of 2, 4, or 8. Individual bytes write mask control An auto precharge function may be enabled to provide a DM Write Latency = 0 self-timed row precharge that is initiated at the end of Auto Refresh and Self Refresh the burst sequence. The refresh functions, either Auto 8192 refresh cycles / 64ms or Self Refresh are easy to use. In addition, 512Mb DDR Precharge & active power down features programmable DLL option. By having a programmable mode register and extended mode Power supplies: VDD & VDDQ = 2.5V 0.2V register, the system can choose the most suitable Operating temperature range modes to maximize its performance. These devices are - Commercial (0 ~ 70C) well suited for applications requiring high memory band - Industrial (-40 ~ 85C) width result in a device particularly well suited to high Interface: SSTL 2 I/O Interface performance main memory and graphics applications. Package: 60-Ball, 8x13x1.2 mm (max) TFBGA - Pb free and Halogen Free All parts are ROHS compliant Table 1.Ordering Information Part Number Clock Data Rate Package Temperature Temp Range AS4C32M16D1-5BCN 200MHz 400Mbps/pin 60 ball TFBGA Commercial 0 ~ 70C Industrial -40 ~ 85C AS4C32M16D1-5BIN 200MHz 400Mbps/pin 60 ball TFBGA B: indicates TSOP II package C: indicates Commercial temp. I: indicates Industrial temp. N: indicates lead free ROHS Confidential 2 Rev. 1.0 Aug. /2014