AS4C32M16D2 512M (32M x 16 bit) DDRII Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.1, Feb. /2013) Overview Features JEDEC Standard Compliant The AS4C32M16D2 DDR2 SDRAM is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous dynamic JEDEC standard 1.8V I/O (SSTL 18-compatible) random-access memory (SDRAM) containing 512 Mbits in Power supplies: V & V = +1.8V 0.1V DD DDQ a 16-bit wide data I/Os. It is internally configured as a quad Supports JEDEC clock jitter specification bank DRAM, 4 banks x 8Mb addresses x 16 I/Os Fully synchronous operation The device is designed to comply with DDR2 DRAM key Fast clock rate: 400 MHz features such as posted CAS with additive latency, Write Differential Clock, CK & CK latency = Read latency -1, Off-Chip Driver (OCD) impedance Bidirectional single/differential data strobe adjustment, and On Die Termination(ODT). All of the control and address inputs are synchronized -DQS & DQS with a pair of externally supplied differential clocks. Inputs 4 internal banks for concurrent operation are latched at the cross point of differential clocks (CK 4-bit prefetch architecture rising and CK falling) Internal pipeline architecture All I/Os are synchronized with a pair of bidirectional Precharge & active power down strobes (DQS and DQS ) in a source synchronous fashion. Programmable Mode & Extended Mode registers The address bus is used to convey row, column, and bank Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5, 6 address information in RAS WRITE latency = READ latency - 1 t , CAS multiplexing style. Accesses begin with the CK registration of a Bank Activate command, and then it is Burst lengths: 4 or 8 followed by a Read or Write command. Read and write Burst type: Sequential / Interleave accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented DLL enable/disable accesses start at a selected location and continue for a Off-Chip Driver (OCD) programmed number of locations in a programmed -Impedance Adjustment sequence. Operating the four memory banks in an -Adjustable data-output drive strength interleaved fashion allows random access operation to On-die termination (ODT) occur at a higher rate than is possible with standard RoHS compliant DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the Auto Refresh and Self Refresh end of the burst sequence. A sequential and gapless data Operating temperature range rate is possible depending on burst length, CAS latency, - Commercial (-0 ~ 85C) and speed grade of the device. - Industrial (-40 ~ 95C) 8192 refresh cycles / 64ms - Average refresh period 7.8s 0 TC +85 3.9s +85 TC +95 84-ball 8x12.5x1.2mm (max) FBGA - Pb and Halogen Free Ordering Information Part Number Clock Frequency Data Rate Package Temperature Temp Range AS4C32M16D2-25BCN 400MHz 800Mbps/pin 84-ball FBGA Commercial -0 ~ 85C AS4C32M16D2-25BIN 400MHz 800Mbps/pin 84-ball FBGA Industrial -40 ~ 95C B: indicates 84-ball (8.0 x 12.5 x 1.2mm) TFBGA package C: indicates Commercial temp. I: indicates Industrial temp. N: indicates Pb and Halogen Free ROHS Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 1 Rev. 1.1 Feb. /2013 AS4C32M16D2 Figure 1. Ball Assignment (FBGA Top View) 1 2 3 7 8 9 VDD NC VSS VSSQ UDQS VDDQ A DQ14 VSSQ UDM UDQS VSSQ DQ15 B . VDDQ DQ9 VDDQ VDDQ DQ8 VDDQ C DQ12 VSSQ DQ11 DQ10 VSSQ DQ13 D VDD NC VSS VSSQ LDQS VDDQ E DQ6 VSSQ LDM LDQS VSSQ DQ7 F VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ G DQ4 VSSQ DQ3 DQ2 VSSQ DQ5 H VDDL VREF VSS VSSDL CK VDD J CKE WE RAS CK ODT K NC BA0 BA1 CAS CS L A10 A1 A2 A0 VDD M VSS A3 A5 A6 A4 N A7 A9 A11 A8 VSS P VDD A12 NC NC NC R Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 2 Rev. 1.1 Feb. /2013