AS4C32M16SB Revision History 54pin TSOPII PACKAGE - Dual Die Package (DDP) AS4C32M16SB-7TCN/AS4C32M16SB-7TIN/AS4C32M16SB-6TIN 54-ball FBGA AS4C32M16SB-7BIN Revision Details Date Rev 1.0 Preliminary datasheet Jun 2016 Rev 1.1 Page 20 -Adjust the values of IDD2P, IDD2PS and IDD6 to 8mA. Sept 2019 Rev 1.2 Mar.2020 Added BGA Package Alliance Memory Inc. 12815 NE 124th Street Suite D,Kirkland WA 98034 USA Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 57 - Rev.1.2. March 2020AS4C32M16SB Overview Features Fast access time from clock: 4.5/5/5.4 ns The 512Mb SDRAM is a high-speed CMOS Fast clock rate: 200/166/143 MHz synchronous DRAM containing 512 Mbits. It is internally configured as 4 Banks of 8M word x 16 Fully synchronous operation DRAM with a synchronous interface (all signals are Internal pipelined architecture registered on the positive edge of the clock signal, 8M word x 16-bit x 4-bank CLK). Read and write accesses to the SDRAM are Programmable Mode registers burst oriented accesses start at a selected location - CAS Latency: 2 or 3 and continue for a programmed number of locations - Burst Length: 1, 2, 4, 8, or full page in a programmed sequence. Accesses begin with the - Burst Type: Sequential or Interleaved registration of a Bank Activate command which is then followed by a Read or Write command. The - Burst stop function SDRAM provides for programmable Read or Write Auto Refresh and Self Refresh burst lengths of 1, 2, 4, 8, or full page, with a burst 8192 refresh cycles/64ms termination option. An auto precharge function may CKE power down mode be enabled to provide a self-timed row precharge that Single +3.3V 0.3V power supply is initiated at the end of the burst sequence. The Operating Temperature Range: refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode - Commercial: T = 0~70C A register, the system can choose the most suitable - Industrial: T = -40~85C A modes to maximize its performance. These devices Interface: LVTTL are well suited for applications requiring high memory 54-pin 400 mil plastic TSOP II package bandwidth and particularly well suited to high - Pb free and Halogen free performance PC applications. 54-ball 8x8x1.2mm(MAX) FBGA - Pb free and Halogen free Table 1. Key Specifications AS4C32M16SB -6/7 tCK3 Clock Cycle time (min.) 6/7 ns 5/5.4 ns tAC3 Access time from CLK (max.) tRAS Row Active time (min.) 42/42 ns tRC Row Cycle time (min.) 60/63 ns Table 2. Ordering Information Package Temperature Temp Range Part Number Frequency AS4C32M16SB-7TCN 143MHz 54 Pin TSOP II Commercial 0C to 70C AS4C32M16SB-7TIN 143MHz 54 Pin TSOP II Industrial -40C to 85C AS4C32M16SB-6TIN 166MHz 54 Pin TSOP II Industrial -40C to 85C AS4C32M16SB-7BIN 143MHz 54 ball FBGA Industrial -40C to 85C Confidential - 2 of 57 - Rev.1.2. March 2020