AS4C32M16SM
512M (32M x 16) bit Synchronous DRAM (SDRAM)
Confidential Preliminary (Rev. 1.0, July /2014)
Revision History AS4C32M16SM
Revision Details Date
Rev 1.0 Preliminary datasheet July 2014
Confidential 1 | P a g e R e v 1 . 0 , J u l y 2014
AS4C32M16SM
512M (32M x 16) bit Synchronous DRAM (SDRAM)
Confidential Preliminary (Rev. 1.0, July /2014)
Features
PC133-compliant
Configurations 32 Meg x 16 (8 Meg x 16 x 4 banks)
Fully synchronous; all signals registered on positive edge of system clock
Internal, pipelined operation; column address can be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge and auto refresh modes
Self refresh mode
Auto refresh64ms, 8192-cycle refresh (commercial and industrial)
LVTTL-compatible inputs and outputs
Single 3.3V 0.3V power supply
Operating temperature range
o Commercial (0C to +70C)
o Industrial (40C to +85C)
Timing cycle time
o 7.5ns @ CL = 3 (PC133)
o 7.5ns @ CL = 2 (PC133)
Plastic package OCPL2
o 54-pin TSOP II (400 mil) Pb-free
All parts ROHS Compliant
Table 1. Key Timing Parameters
Clock Frequency Set up time Hold time Access time t (ns) t (ns)
RCD RP
CL =3
133 MHz 1.5ns 0.8ns 5.4ns 13.75 13.75
CL = CAS (READ) latency
Table 2 Ordering Information
Product part No Org Temperature Package
AS4C32M16SM-7TCN 32M x 16 Commercial 0C to 70C 54-pin TSOP II (400mil)
AS4C32M16SM-7TIN 32M x 16 Industrial -40C to 85C 54-pin TSOP II (400mil)
Table 3 Address Table
Parameter 32M x 16
Configuration 8 Meg x 16 x 4 banks
Refresh Count 8K
Row Addressing 8K A [12:0]
Bank Addressing 4 BA [1:0]
Column Addressing 1K A [9:0]
Confidential 2 | P a g e R e v 1 . 0 , J u l y 2014