AS4C4M16S Revision History AS4C4M16S- 54PIN 400 MIL PLASTIC TSOP II PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet February 2011 Rev 2.0 Removed 6TAN automotive temp May 2014 page 1 and page 52 (see separate datasheet for this option) Added 6TCN 166MHz clock commercial temp May 2014 page 1 and page 52 Added in temperature range to page 1 May 2014 * Operating temperature range - Commercial (0 ~ 70C) - Industrial (-40 ~ 85C) Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM (SDRAM) Rev2.0 May 2014 Alliance Memory Table1. Key Specifications Features AS4C4M16S - 6/7 Fast access time from clock: 5.4/5.4 ns tCK3 Clock Cycle time(min.) 6/7ns Fast clock rate: 166/143 MHz tAC3 Fully synchronous operation Access time from CLK(max.) 5.4/5.4ns Internal pipelined architecture t RAS Row Active time(min.) 42/49 ns 1M word x 16-bit x 4-bank tRC Row Cycle time(min.) 60/63 ns Programmable Mode registers - CAS Latency: 2, or 3 Table 2. Ordering Information - Burst Length: 1, 2, 4, 8, or full page Part Number Frequency Package - Burst Type: interleaved or linear burst - Burst stop function AS4C4M16S-6TCN 166MHz TSOP II Auto Refresh and Self Refresh AS4C4M16S-6TIN 166MHz TSOP II 4096 refresh cycles/64ms AS4C4M16S-7TCN 143MHz TSOP II CKE power down mode Single +3.3V 0.3V power supply T: indicates TSOPII Package, Interface: LVTTL N: indicates Pb and Halogen Free for TSOPII Package 54-pin 400 mil plastic TSOP II package - Pb free and Halogen free Figure 1.Pin Assignment (Top View) VDD 1 54 VSS DQ0 2 53 DQ15 3 52 VDDQ VSSQ Overview DQ1 4 51 DQ14 DQ2 5 50 DQ13 The AS4C4M16S SDRAM is a high-speed CMOS VSSQ 6 49 VDDQ synchronous DRAM containing 64 Mbits. It is DQ3 7 48 DQ12 internally configured as 4 Banks of 1M word x 16 8 47 DQ4 DQ11 DRAM with a synchronous interface (all signals are 9 46 VDDQ VSSQ registered on the positive edge of the clock signal, DQ5 10 45 DQ10 CLK). Read and write accesses to the SDRAM are DQ6 11 44 DQ9 burst oriented accesses st art at a selected location VSSQ 12 43 VDDQ and continue for a programmed number of locations DQ7 13 42 DQ8 in a programmed sequence. Accesses begin with the 14 41 VDD VSS registration of a BankActivate command which is then LDQM 15 40 NC/RFU followed by a Read or Write command. WE 16 39 UDQM The AS4C4M16S provides for programmable Read CAS 17 38 CLK or Write burst lengths of 1, 2, 4, 8, or full page, with a 18 37 RAS CKE burst termination option. An auto precharge function 19 36 CS NC may be enabled to provide a self-timed row precharge 20 35 BA0 A11 that is initiated at the end of the burst sequence. The BA1 21 34 A9 refresh functions, either Auto or Self Refresh are easy A10/AP 22 33 A8 to use. By having a programmable mode register, the A0 23 32 A7 system can choose the most suitable modes to 24 31 A1 A6 maximize its performance. These devices are well 25 30 A2 A5 suited for applications requiring high memory 26 29 A3 A4 bandwidth and particularly well suited to high VDD 27 28 VSS performance PC applications. * Operating temperature range - Commercial (0 ~ 70C) - Industrial (-40 ~ 85C) . 1 Rev2.0 May 2014