AS4C4M16SA-5TCN Revision History AS4C4M16SA-5TCN 54pin-TSOPII PACKAGE Revision Details Date Rev 1.0 Initial Issue Dec. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 54 - Rev.1.0 Dec. 2016AS4C4M16SA-5TCN 4M x 16 bit Synchronous DRAM (SDRAM) Features Overview Fast access time from clock: 4.5ns The AS4C4M16SA SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is Fast clock rate: 200MHz internally configured as 4 Banks of 1M word x 16 Fully synchronous operation DRAM with a synchronous interface (all signals are Internal pipelined architecture registered on the positive edge of the clock signal, 1M word x 16-bit x 4-bank CLK). Read and write accesses to the SDRAM are Programmable Mode registers burst oriented accesses start at a selected location - CAS Latency: 2 or 3 and continue for a programmed number of locations in - Burst Length: 1, 2, 4, 8, or full page a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then - Burst Type: Sequential or Interleaved followed by a Read or Write command. The - Burst stop function EM638165 provides for programmable Read or Write - Optional drive strength control burst lengths of 1, 2, 4, 8, or full page, with a burst Auto Refresh and Self Refresh termination option. An auto precharge function may be 4096 refresh cycles/64ms enabled to provide a self-timed row precharge that is CKE power down mode initiated at the end of the burst sequence. The refresh Single +3.3V 0.3V power supply functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system Operating Temperature: T = 0~70C A can choose the most suitable modes to maximize its Interface: LVTTL performance. These devices are well suited for 54-pin 400 mil plastic TSOP II package applications requiring high memory bandwidth and - Pb free and Halogen free particularly well suited to high performance PC applications. Table 1. Key Specifications AS4C4M16SA -5 tCK3 Clock Cycle time (min.) 5 ns tAC3 Access time from CLK (max.) 4.5 ns tRAS Row Active time (min.) 40 ns tRC Row Cycle time (min.) 55 ns Table 2. Ordering Information Temperature Temp Range Part Number Frequency Package Commercial 0~70 AS4C4M16SA- 5TCN 200 MHz 54 pin TSOP II Confidential - 2 of 54 - Rev.1.0 Dec. 2016