AS4C4M32D1A-5BIN Alliance Memory

AS4C4M32D1A-5BIN AS4C4M32D1A-5BCN Revision History 128Mb AS4C4M32D1A - 144 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet May. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/64 - Rev.1.0 May 2016AS4C4M32D1A-5BIN AS4C4M32D1A-5BCN Features Overview Fast clock rate: 200 MHz The 128Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Differential Clock CK & input CK Mbits. It is internally configured as a quad 1M x 32 4 Bi-directional DQS. Data transactions on both DRAM with a synchronous interface (all signals are edges of DQS (1DQS / Byte) registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and . DLL aligns DQ and DQS transitions CK Read and write accesses to the SDRAM are burst Edge aligned data & DQS output oriented accesses start at a selected location and Center aligned data & DQS inpu continue for a programmed number of locations in a programmed sequence. Accesses begin with the 4 internal banks, 1M x 32-bit for each bank registration of a BankActivate command, which is then Programmable mode and extended mode registers followed by a Read or Write command. The device - CAS Latency: 2, 2.5, 3 provides programmable Read or Write burst lengths of - Burst length: 2, 4, 8 2, 4, 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the - Burst Type: Sequential & Interleave end of the burst sequence. The refresh functions, either All inputs except DQs & DM are at the positive Auto or Self Refresh are easy to use. In addition, 128Mb edge of the system clock DDR SDRAM features programmable DLL option. By 4 individual DM control for write masking only having a programmable mode register and extended mode register, the system can choose the most suitable Auto Refresh and Self Refresh modes to maximize its performance. These devices are 4096 refresh cycles / 64ms well suited for applications requiring high memory Operating Temperature: bandwidth result in a device particularly well suited to high performance main memory and graphics - Industrial -40 C~85 C applications. - Commercial 0C to 70C Power supplies: VDD & VDDQ = 2.5V 0.2V Interface: SSTL 2 I/O compatible 144-ball 12 x 12 x 1.4mm LFBGA package -Pb and Halogen Free Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C4M32D1A-5BCN 4Mx32 Commercial 0C to 70C 200 144-ball FBGA AS4C4M32D1A-5BIN 4Mx32 Industrial -40C to 85C 200 144-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR1-400 200MHz 3 15 15 Confidential - 2/64 - Rev.1.0 May 2016