AS4C4M32MSA-6BINTR Alliance Memory

AS4C4M32MSA-6BIN Revision History 128M (4M x 32) /RZ 3RZHU 6 5 0 AS4C40 3206 90ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Dec. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 47 - Rev.1.0 Dec. 2017AS4C4M32MSA-6BIN 128M(4Mx32) Low Power SDRAM Features - LVCMOS Compatible IO Interface - Functionality - 90 ball FBGA with 0.8 mm ball pitch (8mm x 13mm) - Standard SDRAM Functionality - AS4C4M32MSA : Pb-Free & Halogen Free - Programmable burst lengths : 1, 2, 4, 8 or full page - 64ms refresh period (4K cycle) - JEDEC Compatibility Functional Description - Low Power Features The AS4C4M32MSA Family is high-performance CMOS - Auto TCSR(Temperature Compensated Self Refresh) Dynamic RAMs (DRAM) organized as 4M x 32. These - Partial Array Self Refresh power-saving mode devices feature advanced circuit design to provide low active - Deep Power Down Mode current and extremely low standby current. - Driver Strength Control The device is compatible with the JEDEC standard - Operating Temperature Ranges: LP-SDRAM specifications. - Industrial (-40 to +85) Table I.Ordering Information Temperature Org Max Clock (MHz) Product part No Package 166 MHz Industrial -40C to 85C AS4C4M32MSA-6BIN 4M x 32 90-ball FBGA Table II.Key Specifications AS4C4M32MSA-6BIN -6 tCK(3) Clock Cycle time(min.) 6ns tAC(3) Access time from CLK (max.) 5.5ns tRAS Row Active time(min.) 48 ns Row Cycle time(min.) tRC 60ns Confidential - 2 of 47 - Rev.1.0 Dec. 2017