8Gb: x4, x8, x16 DDR3L SDRAM Description Revision History 8Gb: x4, x8, x16 DDR3L SDRAM AS4C2GM4D3L 256 Meg x 4 x 8 banks* AS4C1G8MD3L 128 Meg x 8 x 8 banks AS4C512M16D3L 64 Meg x 16 x 8 banks Revision Details Date Rev 1.0 Preliminary datasheet February 2016 Rev 2.0 Amend Table 1 noted. June 2016 * not released yet Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 0C 8Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM AS4C2GM4D3L 256 Meg x 4 x 8 banks * AS4C1G8MD3L 128 Meg x 8 x 8 banks AS4C512M16D3L 64 Meg x 16 x 8 banks T of 0C to +95C C Features 64ms, 8192-cycle refresh at 0C to +85C V = V = 1.35V (1.2831.45V) DD DDQ 32ms at +85C to +95C Backward compatible to V = V = 1.5V 0.075V DD DDQ Self refresh temperature (SRT) Supports DDR3L devices to be backward com- Automatic self refresh (ASR) patible in 1.5V applications Write leveling Differential bidirectional data strobe Multipurpose register 8n-bit prefetch architecture Output driver calibration Differential clock inputs (CK, CK ) 8 internal banks Options Marking Nominal and dynamic on-die termination (ODT) Configuration for data, strobe, and mask signals 2 Gig x 4 2GM4 Programmable CAS (READ) latency (CL) 1 Gig x 8 1GM 8 Programmable posted CAS additive latency (AL) 512 Meg x 16 512M16 Programmable CAS (WRITE) latency (CWL) FBGA package (Pb-free) x4, x8 Fixed burst length (BL) of 8 and burst chop (BC) of 4 78-ball (9mm x 13.2mm) B (via the mode register set MRS ) FBGA package (Pb-free) x16 Selectable BC4 or BL8 on-the-fly (OTF) 96-ball (9mm x 14mm) B Self refresh mode Timing cycle time 938ps CL = 14 (DDR3-2133) -09 1.07ns CL = 13 (DDR3-1866) -10 1.25ns CL = 11 (DDR3-1600) -12 Operating temperature Commercial (0C T +95C) C Industrial (40C T +95C) I C Key Timing Parameters t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) -12 1600 11-11-11 13.75 13.75 13.75 Table 1:Ordering Information Part Number Clock Frequency Data Rate(MT/s) Power Supply Package AS4C2GM4D3L-12BCN * 800 MHz 1600 1.35V (1.2831.45V) 78-ball (9mm x 13.2mm) FBGA AS4C2GM4D3L-12BIN * 1600 78-ball (9mm x 13.2mm) FBGA 800 MHz 1.35V (1.2831.45V) AS 4C1G8 MD3L-12BCN 800 MHz 1600 1.35V (1.2831.45V) 78-ball (9mm x 13.2mm) FBGA AS 4C1G8 MD3L-12BIN 800 MHz 1600 1.35V (1.2831.45V) 78-ball (9mm x 13.2mm) FBGA 800 MHz AS4C512M16D3L-12BCN 1600 1.35V (1.2831.45V) 96-ball (9mm x 14mm) FBGA 800 MHz AS4C512M16D3L-12BIN 1600 96-ball (9mm x 14mm) FBGA 1.35V (1.2831.45V) Alliance Memory Inc will only offer the -12 1.25ns CL = 11 (DDR3-1600) option Notes: 1. 2.* not released yet Rev 2.0 June 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 1 2015 Alliance Memory, Inc. All rights reserved. TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice