AS4C512M16D3LB-12BCN Alliance Memory

AS4C512M16D3LB Revision History 8Gbit DDR3L AS4C512M16D3LB 8 BANKS X 64Mbit X 16 Dual Die Package (DDP) 96ball FBGA Package Revision Details Date Rev 1.0 Preliminary datasheet May 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0 May 2019AS4C512M16D3LB 512M x 16 bit DDR3L Synchronous DRAM (SDRAM) Features Overview JEDEC Standard Compliant The 8Gb Double-Data-Rate-3L DRAMs is double data rate architecture to achieve high-speed operation. It is Power supplies: V & V = +1.35V DD DDQ internally configured as an eight bank DRAM. Backward compatible to V & V = +1.5V 0.075V DD DDQ The 8Gb chip is organized as 64Mbit x 16 I/Os x 8 bank Operating temperature: devices. These synchronous devices achieve high Commercial: T = 0~95 C C speed double-data-rate transfer rates of up to 1600 Mb/ Industrial: T = -40~95 C C sec/pin for general applications. Supports JEDEC clock jitter specification The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address Fully synchronous operation inputs are synchronized with a pair of externally supplied Fast clock rate: 800MHz differential clocks. Inputs are latched at the cross point of Differential Clock, CK & CK differential clocks (CK rising and CK falling). All I/Os are Bidirectional differential data strobe synchronized with differential DQS pair in a source - DQS & DQS synchronous fashion. 8 internal banks for concurrent operation These devices operate with a single +1.35V -0.067V / 8n-bit prefetch architecture +0.1V power supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at -40C T +85 C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh Package: Two 512Mbit x 8 dies stacked (DDP) 96-ball 9 x 13.5 x 1.2mm FBGA package ROHS Compliant - Pb and Halogen Free Table 1. Ordering Information Org Temperature Max Clock (MHz) Product part No Package 800 AS4C512M16D3LB-12BCN 512M x 16 96-ball FBGA Commercial 0C to 95C 800 96-ball FBGA AS4C512M16D3LB-12BIN 512M x 16 Industrial -40C to 95C Table 2. Speed Grade Information CAS Latency tRCD(ns) Speed Grade tRP(ns) Clock Frequency DDR3L-1600 800 MHz 11 13.75 13.75 Confidential - 2 of 86 - Rev.1.0 May 2019