AS4C512M4D3LC-12BCN Alliance Memory

AS4C512M4D3LC-12BCN Revision History 512M x 4 bit DDR3L AS4C512M4D3LC - 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet July 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 86 - Rev.1.0. July 2019AS4C512M4D3LC-12BCN 512M x 4 bit DDR3L Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jul. /2019) Features Overview JEDEC Standard Compliant The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V (1.283V~1.45V) DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = +1.5V 0.075V DD DDQ DRAM. Operating temperature range: The 2Gb chip is organized as 64Mbit x 4 I/Os x 8 bank - Normal operating temperature: TC = 0~85 C devices. These synchronous devices achieve high speed - Extended temperature: T = 85~95 C C double-data-rate transfer rates of up to 1600 Mb/sec/pin Supports JEDEC clock jitter specification for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are Fast clock rate: 800MHz synchronized with a pair of externally supplied differential Differential Clock, CK & CK clocks. Inputs are latched at the cross point of differential Bidirectional differential data strobe clocks (CK rising and CK falling). All I/Os are synchronized - DQS & DQS with differential DQS pair in a source synchronous fashion. 8 internal banks for concurrent operation These devices operate with a single 1.35V -0.067V/ 8n-bit prefetch architecture +0.1V power supply and are available in BGA packages. Pipelined internal architecture Precharge & active power down Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control Average refresh period - 8192 cycles/64ms (7.8us at 0C T +85C) C - 8192 cycles/32ms (3.9us at +85C T +95C) C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 7.5 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Org Temperature Max Clock (MHz) Product part No Package Commercial (Extended) 800 78-ball FBGA 512M x 4 AS4C512M4D3LC-12BCN 0C to 95C Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3 L-1600 Confidential - 2 of 86 - Rev.1.0. July 2019