AS4C512M8D3L-12BCN Alliance Memory

4Gb DDR3L - AS4C512M8D3L Revision History AS4C512M8D3L - 78-ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet April 2014 Rev 2.0 AddedBackward compatible to VDD & VDDQ = 1.5V +/- August 2014 0.075 - page 2 Updated Table 12. Recommended DC Operating Conditions page 21 Added CL=5 & CL=6 to Table 18 page 26 Confidential 1 Rev. 2.0 Aug. /2014 4Gb DDR3L - AS4C512M8D3L 512M x 8 bit DDR3L Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 2.0, Aug. /2014) Overview Features JEDEC Standard Compliant The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = 1.5V 0.075V DD DDQ DRAM. Operating temperature: The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank - Commercial (Extended) (0 ~ 95C) devices. These synchronous devices achieve high - Industrial (-40 ~ 95C) speed double-data-rate transfer rates of up to 1600 Supports JEDEC clock jitter specification Mb/sec/pin for general applications. Fully synchronous operation The chip is designed to comply with all key DDR3L Fast clock rate: 800MHz DRAM key features and all of the control and address inputs are synchronized with a pair of externally Differential Clock, CK & CK supplied differential clocks. Inputs are latched at the Bidirectional differential data strobe cross point of differential clocks (CK rising and CK - DQS & DQS falling). All I/Os are synchronized with differential DQS 8 internal banks for concurrent operation pair in a source synchronous fashion. 8n-bit prefetch architecture These devices operate with a single 1.35V -0.067V Internal pipeline architecture /+0.1V power supply and are available in BGA Precharge & active power down packages. Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s -40 TC +85 3.9s +85 TC +95 Write Leveling OCD Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 9 x 10.5 x 1.2mm FBGA package - All parts are ROHS Compliant Table 1. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR3L-1600 800 MHz 11 13.75 13.75 Table 2. Ordering Information Product part No Org Temperature Package AS4C512M8D3L-12BCN 512M x 8 Commercial (Extended) 78-ball FBGA 0C to 95C AS4C512M8D3L-12BIN 512M x 8 Industrial 78-ball FBGA -40C to 95C (Extended) Confidential 2 Rev. 2.0 Aug. /2014