AS4C512M8D3LA-12BCN Alliance Memory

AS4C512M8D3LA-12BCN Revision History 4Gb AS4C512M8D3LA-12BCN - 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet May. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -183- Rev. 1.0 May 2016AS4C512M8D3LA-12BCN 512M x 8 bit DDR3L Synchronous DRAM (SDRAM) Features Overview JEDEC Standard Compliant The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed Power supplies: V & V = +1.35V DD DDQ operation. It is internally configured as an eight bank Backward compatible to V & V = 1.5V 0.075V DD DDQ DRAM. Operating temperature: 0~95 C (TC) The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank Supports JEDEC clock jitter specification devices. These synchronous devices achieve high Fully synchronous operation speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. Fast clock rate: 800MHz The chip is designed to comply with all key DDR3L Differential Clock, CK & CK DRAM key features and all of the control and address Bidirectional differential data strobe inputs are synchronized with a pair of externally - DQS & DQS supplied differential clocks. Inputs are latched at the 8 internal banks for concurrent operation cross point of differential clocks (CK rising and CK 8n-bit prefetch architecture falling). All I/Os are synchronized with differential DQS Pipelined internal architecture pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V Precharge & active power down /+0.1V power supply and are available in BGA packages. Programmable Mode & Extended Mode registers Additive Latency (AL): 0, CL-1, CL-2 Programmable Burst lengths: 4, 8 Burst type: Sequential / Interleave Output Driver Impedance Control 8192 refresh cycles / 64ms - Average refresh period 7.8s 0C TC +85C 3.9s +85C TC +95C Write Leveling ZQ Calibration Dynamic ODT (Rtt Nom & Rtt WR) RoHS compliant Auto Refresh and Self Refresh 78-ball 9 x 10.5 x 1.0mm FBGA package - Pb and Halogen Free Table 1. Ordering Information Temperature Max Clock (MHz) Org Product part No Package Commercial 0C to 95C AS4C512M8D3LA-12BCN 800 78-ball FBGA 512M x 8 Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP 13.75 13.75 800 MHz 11 DDR3L-1600 Confidential -283- Rev. 1.0 May 2016