AS4C512M8D4-75BCNTR Alliance Memory

AS4C512M8D4 Revision History 4Gb DDR4 AS4C512M8D4 - 78 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Aug 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 196 - Rev.1.0. Aug.2019AS4C512M8D4 512M x 8 bit DDR4 Synchronous DRAM (SDRAM) Preliminary (Rev. 1.0, Aug. /2019) Features JEDEC Standard Compliant Internal V Training REFDQ Fast clock rate: 1200/1333MHz Read Preamble Training Power supplies: Control Gear Down Mode - V & V = +1.2V 0.06V DD DDQ Per DRAM Addressability (PDA) - V = +2.5V -0.125V / +0.25V PP Output Driver Impedance Control Operating temperature: Dynamic on-die termination (ODT) - Commercial : T = 0~95 C C Input Data Mask (DM) and Data Bus Inversion (DBI) - Industrial: TC = -40~95 C ZQ Calibration Supports JEDEC clock jitter specification Command/Address latency (CAL) Bidirectional differential data strobe, DQS &DQS Maximum Power Saving Mode (MPSM) Differential Clock, CK & CK Asynchronous Reset 16 internal banks: 4 groups of 4 banks each DLL enable/disable Separated IO gating structures by Bank Group Burst Length (BL8/BC4/BC4 or 8 on the fly) 8n-bit prefetch architecture Burst type: Sequential / Interleave Precharge & Active power down CAS Latency (CL) Auto Refresh and Self Refresh CAS Write Latency (CWL) Low-power auto self refresh (LPASR) Additive Latency (AL): 0, CL-1, CL-2 Self Refresh Abort Average refresh period Fine Granularity Refresh - 8192 cycles/64ms (7.8us at -40C T +85C) C Dynamic ODT (RTT PARK & RTT Nom & RTT WR) - 8192 cycles/32ms (3.9us at +85C T +95C) C Data Interface: Pseudo Open Drain (POD) Write Leveling RoHS compliant DQ Training via MPR Hard post package repair (hPPR) Programmable preamble is supported both of 1t CK and 2t mode CK Soft post package repair (sPPR) Command/Address (CA) Parity Package: Pb Free and Halogen Free Data bus write cyclic redundancy check (CRC) - 78-ball 7.5 x 10.6 x 1.2mm FBGA Table 1. Ordering Information Product part No Org Temperature Max Clock (MHz) Package Commercial (Extended) 512M x 8 78-ball FBGA AS4C512M8D4-83BCN 1200 0C to 95C AS4C512M8D4-83BIN 512M x 8 Industrial -40C to 95C 78-ball FBGA 1200 Commercial (Extended) 512M x 8 78-ball FBGA AS4C512M8D4-75BCN 1333 0C to 95C AS4C512M8D4-75BIN 512M x 8 Industrial -40C to 95C 78-ball FBGA 1333 Table 2. Speed Grade Information tRCD(ns) Speed Grade CAS Latency Clock Frequency tRP(ns) DDR4-2400 1200 MHz 17 14.16 14.16 DDR4-2666 1333 MHz 19 14.25 14.25 Confidential - 2 of 196 - Rev.1.0. Aug.2019