AS4C64M16D2 1Gb (64M x 16 bit) DDRII Synchronous DRAM (SDRAM) Alliance Memory Confidential Advanced (Rev. 1.0 April 2012) Overview Features The AS4C64M16D2 is a high-speed CMOS Double- Data- JEDEC Standard Compliant Rate-Two (DDR2), synchronous dynamic random JEDEC standard 1.8V I/O (SSTL 18-compatible) - access memory (SDRAM) containing 1024 Mbits in a 16- Power supplies: V & V = +1.8V 0.1V DD DDQ bit wide data I/Os. It is internally configured as a 8- bank Operating temperature: DRAM, 8 banks x 8Mb addresses x 16 I/Os. - Commercial (0 ~ 85C) The device is designed to comply with DDR2 DRAM key - Industrial (-40 ~ 95C) features such as posted CAS with additive latency, Write Supports JEDEC clock jitter specification latency = Read latency -1 and On Die Termination(ODT). Fully synchronous operation All of the control and address inputs are Fast clock rate: 400MHz synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential Differential Clock, CK & CK clocks (CK rising and CK falling) Bidirectional single/differential data strobe All I/Os are synchronized with a pair of bidirectional -DQS & DQS strobes (DQS and DQS ) in a source synchronous fashion. 8 internal banks for concurrent operation The address bus is used to convey row, column, and bank 4-bit prefetch architecture address information in RAS , CAS multiplexing style. Internal pipeline architecture Accesses begin with the registration of a Bank Activate Precharge & active power down command, and then it is followed by a Read or Write Programmable Mode & Extended Mode registers command. Read and write accesses to the DDR2 SDRAM Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5, 6 are 4 or 8-bit burst oriented accesses start at a selected WRITE latency = READ latency - 1 t CK location and continue for a programmed number of Burst lengths: 4 or 8 locations in a programmed sequence. Burst type: Sequential / Interleave Operating the eight memory banks in an interleaved DLL enable/disable fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto On-die termination (ODT) precharge function may be enabled to provide a self- RoHS compliant timed row precharge that is initiated at the end of the Auto Refresh and Self Refresh burst sequence. A sequential and gapless data rate is 8192 refresh cycles / 64ms possible depending on burst length, CAS latency, and -Average refresh period 7.8s 0 TC +85 speed grade of the device. 3.9s +85 TC +95 84-ball 8 x 12.5 x 1.2mm (max) FBGA package - Pb and Halogen Free Table 1. Ordering Information Part Number Clock Frequency Data Rate Power Supply Package AS4C64M16D2-25BCN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V FBGA AS4C64M16D2-25BIN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V FBGA B: indicates 84-ball (8.0 x 12.5 x 1.2mm) FBGA package C: indicates commercial temperature I: indicates industrial temperature N: indicates Pb and Halogen Free ROHS Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR2-800 400 MHz 5 12.5 12.5 Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 1 Rev. 1.1 April. /2012 AS4C64M16D2 Figure 1> Ball Assignment (FBGA Top View) Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 2 Rev. 1.1 April. /2012