AS4C64M16D2A-25BAN Revision History 1Gb Auto-AS4C64M 16D2A - 84 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Jan 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 62 - Rev.1.0 Jan. 2018AS4C64M16D2A-25BAN 64M x 16 bit DDRII Synchronous DRAM (SDRAM) Advance (Rev. 1.0, Jan. /2018) Features Overview JEDEC Standard Compliant The AS4C64M16D2A is a high-speed CMOS Double- Data-Rate-Two (DDR2), synchronous dynamic random- AEC-Q100 Compliant access memory (SDRAM) containing 1024 Mbits in a JEDEC standard 1.8V I/O (SSTL 18-compatible) 16-bit wide data I/Os. It is internally configured as a 8- Power supplies: V & V = +1.8V 0.1V DD DDQ bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The Operating temperature: T = -40~105 C (Automotive) C device is designed to comply with DDR2 DRAM key Supports JEDEC clock jitter specification features such as posted CAS with additive latency, Fully synchronous operation Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination(ODT). Fast clock rate: 400 MHz All of the control and address inputs are synchronized Differential Clock, CK & CK with a pair of externally supplied differential clocks. Inputs Bidirectional single/differential data strobe are latched at the cross point of differential clocks (CK - DQS & DQS rising and CK falling) All I/Os are synchronized with a 8 internal banks for concurrent operation pair of bidirectional strobes (DQS and DQS ) in a source 4-bit prefetch architecture synchronous fashion. The address bus is used to convey Internal pipeline architecture row, column, and bank address information in RAS , CAS multiplexing style. Accesses begin with the registration Precharge & active power down of a Bank Activate command, and then it is followed by Programmable Mode & Extended Mode registers a Read or Write command. Read and write accesses to Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5 the DDR2 SDRAM are 4 or 8-bit burst oriented accesses WRITE latency = READ latency - 1 t CK start at a selected location and continue for a programmed Burst lengths: 4 or 8 number of locations in a programmed sequence. Operating Burst type: Sequential / Interleave the eight memory banks in an interleaved fashion allows DLL enable/disable random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge Off-Chip Driver (OCD) function may be enabled to provide a self-timed row - Impedance Adjustment precharge that is initiated at the end of the burst sequence. - Adjustable data-output drive strength A sequential and gapless data rate is possible depending On-die termination (ODT) on burst length, CAS latency, and speed grade of the RoHS compliant device. Auto Refresh and Self Refresh - Not Support self refresh function with TC > 95C Average refresh period - 8192 cycles/64ms (7.8us at -40 C T +85C) C - 8192 cycles/16ms (1.95us at +85 C TC +105 C) 84-ball 8 x 12.5 x 1.2mm (max) FBGA package - Pb and Halogen Free Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package Automotive -40C to +105C 400 84-ball FBGA AS4C64M16D2A-25BAN 64Mx16 Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR2-800 400MHz 5 12.5 12.5 Confidential - 2 of 62 - Rev.1.0 Jan. 2018