AS4C64M16D2B-25BCN Revision History 1Gb AS4C64M16D2 B-25BCN 84 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Apr. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 69 - Rev.1.0 April 2017AS4C64M16D2B-25BCN Features Description - High speed data transfer rates with system frequency up to The AS4C64M16D2B-25BCN is an eight bank DDR 400 MHz DRAM organized as 8 banks x 8Mbit x 16 (168). The AS4C64M16D2B-25BCN achieves high - 8 internal banks for concurrent operation speed data transfer rates by employing a chip - 4-bit prefetch architecture architecture that prefetches multiple bits and then - Programmable CAS Latency: 3, 4 ,5 , 6 and 7 synchronizes the output data to a system clock. - Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6 - Write Latency = Read Latency -1 The chip is designed to comply with the following key - Programmable Wrap Sequence: Sequential or Interleave DDR2 SDRAM features:(1) posted CAS with additive - Programmable Burst Length: 4 and 8 latency, (2) write latency = read latency-1, (3) On Die - Automatic and Controlled Precharge Command Termination. - Power Down Mode All of the control, address, circuits are synchronized - Auto Refresh and Self Refresh with the positive edge of an externally supplied clock. I/O s o o - Refresh Interval: 7.8 us at 0 C Tcase 85 C, are synchro-nized with a pair of bidirectional strobes (DQS, o o 3.9 us at 85 C < Tcase 105 C DQS) in a source synchronous fashion. - ODT (On-Die Termination) Operating the eight memory banks in an interleaved - Weak Strength Data-Output Driver Option fashion allows random access operation to occur at a - Bidirectional differential Data Strobe (Single-ended data- higher rate than is possible with standard DRAMs. A strobe is an optional feature) sequential and gapless data rate is possible depending - On-Chip DLL aligns DQ and DQs transitions with CK transi- on burst length, CAS latency and speed grade of the tions device. - DQS can be disabled for single-ended data strobe - Differential clock inputs CK and CK - JEDEC Power Supply 1.8V 0.1V - VDDQ =1.8V 0.1V - Available in 84-ball FBGA for x16 component - RoHS compliant - PASR Partial Array Self Refresh - tRAS lockout supported - Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package AS4C64M16D2B-25BCN 400 MHz Commercial 0C to +95C 64Mx16 84-ball FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR2-800 5 12.5 12.5 400 MHz Confidential - 2 of 69 - Rev.1.0 April 2017