512M DDR1-AS4C64M8D1 Revision History AS4C64M8D1-66pin TSOPII and 60-ball TFBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet D 201 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1- Rev.1.0 May 2015512M DDR1-AS4C64M8D1 Features Fast clock rate: 250/200MHz Differential Clock CK & CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 16M x 8-bit for each bank Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved Individual byte write mask control DM Write Latency = 0 Auto Refresh and Self Refresh 8192 refresh cycles / 64ms Precharge & active power down Power supplies: VDD & VDDQ = 2.5V 0.2V Operating Temperature: - Commercial (0~70 C) - Industrial (-40~85 C) Interface: SSTL 2 I/O Interface Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb and Halogen free Package: 60-Ball, 8x13x1.2 mm (max) TFBGA - Pb free and Halogen Free Confidential -2- Rev.1.0 May 2015