AS4C64M8D2-25BIN AS4C64M8D2-25BCN Revision History 512M AS4C64M8D2 60 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Feb. 2014 Rev 1.1 Adjust the temperature value June. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 60 - Rev.1.1 Jun. 2017AS4C64M8D2-25BIN AS4C64M8D2-25BCN 512M (64M x 8 bit) DDRII Synchronous DRAM (SDRAM) Overview Features JEDEC Standard Compliant The 512Mb DDR2 SDRAM is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous dynamic JEDEC standard 1.8V I/O (SSTL 18-compatible) random - access memory (SDRAM) containing 512 Power supplies: V & V = +1.8V 0.1V DD DDQ Mbits in an 8-bit wide data I/Os. It is internally Operating temperature: configured as a quad bank DRAM, 4 banks x 16Mb - Commercial (0 ~ 85 C) addresses x 8 I/Os. - Industrial (-40 ~ 95 C) The device is designed to comply with DDR2 DRAM key features such as posted CAS with additive latency, Supports JEDEC clock jitter specification Write latency = Read latency -1 and On Die Fully synchronous operation Termination(ODT). Fast clock rate: 400 MHz All of the control and address inputs are Differential Clock, CK & CK synchronized with a pair of externally supplied Bidirectional single/differential data strobe differential clocks. Inputs are latched at the cross point 4 internal banks for concurrent operation of differential clocks (CK rising and CK falling) All I/Os are synchronized with a pair of bidirectional 4-bit prefetch architecture strobes (DQS and DQS ) in a source synchronous Internal pipeline architecture fashion. The address bus is used to convey row, Precharge & active power down column, and bank address information in RAS , CAS Programmable Mode & Extended Mode registers multiplexing style. Accesses begin with the registration Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5 of a Bank Activate command, and then it is followed by WRITE latency = READ latency - 1 t CK a Read or Write command. Read and write accesses to Burst lengths: 4 or 8 the DDR2 SDRAM are 4 or 8-bit burst oriented accesses start at a selected location and continue for a Burst type: Sequential / Interleave programmed number of locations in a programmed DLL enable/disable sequence. On-die termination (ODT) Operating the four memory banks in an interleaved RoHS compliant fashion allows random access operation to occur at a Auto Refresh and Self Refresh higher rate than is possible with standard DRAMs. An 8192 refresh cycles / 64ms auto precharge function may be enabled to provide a -Average refresh period self-timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate 7.8s -40 TC +85 is possible depending on burst length, CAS latency, and 3.9s +85 TC +95 speed grade of the device 60-ball 8 x 10 x 1.2mm (max) FBGA package - All parts are ROHS Compliant Table 1. Ordering Information Temperature Org Part Number Max Clock (MHz) Package Commercial 0C to 85C 64Mx 8 400 60 ball FBGA AS4C64M8D2-25BCN 64Mx 8 Industrial -40C to 95C 60 ball FBGA AS4C64M8D2-25BIN 400 B: indicates 60-ball 8 x 10 x 1.2mm (max) FBGA package C: indicates commercial temperature I: indicates industrial temperature N: indicates Pb and Halogen Free - ROHS Compliant Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency t (ns) t (ns) RCD RP DDR2-800 400 MHz 5 12.5 12.5 Confidential - 2 of 60 - Rev.1.1 Jun. 2017