AS4C8M16S 128M - 8M x 16 bit Synchronous DRAM (SDRAM) Confidential (Rev. 2, Feb. /2014) Features Overview Fast access time from clock: 5/5.4 ns The 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is Fast clock rate: 166/143 MHz internally configured as 4 Banks of 2M word x 16 Fully synchronous operation DRAM with a synchronous interface (all signals are Internal pipelined architecture registered on the positive edge of the clock signal, 2M word x 16-bit x 4-bank CLK). Read and write accesses to the SDRAM are Programmable Mode registers burst oriented accesses start at a selected location - CAS Latency: 2, or 3 and continue for a programmed number of locations - Burst Length: 1, 2, 4, 8, or full page in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then - Burst Type: Sequential or Interleaved followed by a Read or Write command. - Burst stop function Auto Refresh and Self Refresh The SDRAM provides for programmable Read or 4096 refresh cycles/64ms Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function CKE power down mode may be enabled to provide a self-timed row precharge Single +3.3V 0.3V power supply that is initiated at the end of the burst sequence. The Interface: LVTTL refresh functions, either Auto or Self Refresh are easy Operating temperature range to use. By having a programmable mode register, the - Commercial (0 ~ 70C) system can choose the most suitable modes to - Industrial (-40 ~ 85C) maximize its performance. These devices are well - Automotive A2 (-40 ~ 105C) suited for applications requiring high memory bandwidth and particularly well suited to high 54-pin 400 mil plastic TSOP II package performance PC applications. 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package All parts ROHS Compliant Table 1. Key Specifications AS4C16M16S -6/7 tCK3 Clock Cycle time (min.) 6/7 ns tAC3 Access time from CLK (max.) 5.4/5.4 ns tRAS Row Active time (min.) 42/42 ns tRC Row Cycle time (min.) 60/63 ns Table 2. Ordering Information Part Number Frequency Package AS4C8M16S-7TCN 143 MHz 54 pin TSOP II AS4C8M16S-6TCN 166 MHz 54 pin TSOP II AS4C8M16S-6TIN 166 MHz 54 pin TSOP II AS4C8M16S-6BIN 166 MHz 54 ball TFBGA AS4C8M16S-7BCN 143 MHz 54 ball TFBGA AS4C8M16S-6TAN 166 MHz 54 pin TSOP II T : indicates TSOP II package B : indicates TFBGA package N : indicates Pb free and Halogen free ROHS compliant parts C: Commercial I: Industrial A: Automotive temperatures Confidential 1 Rev. 2 Feb. /2014 AS4C8M16S Figure 1.1 Pin Assignment (Top View) Figure 1.2 Ball Assignment (Top View) 1 2 3 7 8 9 VDD 1 54 VSS DQ0 2 53 DQ15 VSS DQ15 VSSQ VDDQ DQ0 VDD A 3 52 VDDQ VSSQ DQ1 4 51 DQ14 DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 B DQ2 5 50 DQ13 VSSQ 6 49 VDDQ D Q12 DQ11 VSSQ VD DQ DQ4 DQ3 C DQ3 7 48 DQ12 DQ4 8 47 DQ11 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 D 9 46 VDDQ VSSQ DQ5 10 45 DQ10 DQ8 NC VSS VDD LDQM DQ7 E DQ6 11 44 DQ9 VSSQ 12 43 VDDQ F UDQM CLK CKE CAS RAS WE DQ7 13 42 DQ8 VDD 14 41 VSS NC A11 A9 BA0 BA1 CS G 15 40 LDQM NC/RFU WE 16 39 UDQM A 8 A7 A6 A 0 A1 A10 H CAS 17 38 CLK RAS 18 37 CKE CS 19 36 NC VSS A5 A4 A3 A2 VDD J BA0 20 35 A11 BA1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS Confidential 2 Rev. 2 Feb. /2014