FEBRUARY 2011 AS4C8M16S 128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM) Alliance Memory Table1. Key Specifications Features AS4C8M16S - 6/7 Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz tCK3 Clock Cycle time(min.) 6/7 ns Fully synchronous operation tAC3 Access time from CLK(max.) 5/5.4 ns Internal pipelined architecture tRAS Row Active time(min.) 42/42 ns 2M word x 16-bit x 4-bank tRC Row Cycle time(min.) 60/63 ns Programmable Mode registers o CAS Latency: 2, or 3 Table 2. Ordering Information o Burst Length: 1, 2, 4, 8, or full page Part Number Frequency Package o Burst Type: interleaved or linear burst AS4C8M16S -6TCN 166MHz TSOP II o Burst stop function Auto Refresh and Self Refresh AS4C8M16S-6TIN 166MHz TSOP II Operating temperature range AS4C8M16S -7TCN 143MHz TSOP II o Commercial (0 ~ 70C) o Industrial (-40 ~ 85C) AS4C8M16S-7BCN 143MHz TFBGA 4096 refresh cycles/64ms AS4C8M16S-6BIN 166MHz TFBGA CKE power down mode T: indicates TSOPII Package, Single +3.3V 0.3V power supply N: indicates Pb and Halogen Free for TSOPII Package B: indicates BGA package Interface: LVTTL C: commercial I:industrial temperatures 54-pin 400 mil plastic TSOP II package 54-ball 8.0 x 8.0 x 1.2mm(max) FBGA package Pb free and Halogen free Figure 1. Pin Assignment (Top View) Overview VDD 1 54 VSS DQ0 2 53 DQ15 The AS4C8M16S SDRAM is a high-speed CMOS synchronous VDDQ 3 52 VSSQ DRAM containing 128 Mbits. It is internally configured as 4 51 DQ1 4 DQ14 Banks of 2M word x 16 DRAM with a synchronous interface 5 50 DQ2 DQ13 6 49 (all signals are registered on the positive edge of the clock VSSQ VDDQ DQ3 7 48 DQ12 signal, CLK) . Read and write accesses to the SDRAM are 8 47 DQ4 DQ11 burst oriented accesses start at a selected location and 9 46 VDDQ VSSQ continue for a programmed number of locations in a 10 45 DQ5 DQ10 programmed sequence. Accesses begin with the registration DQ6 11 44 DQ9 of a BankActivate command which is then followed by a 12 43 VSSQ VDDQ Read or Write command. 13 42 DQ7 DQ8 14 41 VDD VSS The AS4C8M16S provides for programmable Read or 15 40 LDQM NC/RFU Write burst lengths of 1, 2, 4, 8, or full page, with a burst 16 39 WE UDQM termination option. An auto precharge function may be 17 38 CAS CLK enabled to provide a self- timed row precharge that is 18 37 RAS CKE initiated at the end of the burst sequence. The refresh 19 36 CS NC functions, either Auto or Self Refresh are easy to use. 20 35 BA0 A11 21 34 BA1 A9 By having a programmable mode register, the system 22 33 A10/AP A8 can choose the most suitable modes to maximize its 23 32 A0 A7 performance. These devices are well suited for applications 24 31 A6 A1 requiring high memory bandwidth and particularly well 25 30 A2 A5 suited to high performance PC applications. 26 29 A4 A3 27 28 VSS VDD 1 AS4C8M16S FEBRUARY 2011 Figure 2. Block Diagram BUFFER 2M x 16 CELL ARRAY (BANK A) CKE Column Decoder CS RAS COMMAND DQ0 DECODER DQ Buffer CONTROL CAS SIGNAL WE DQ15 GENERATOR LDQM, UDQM COLUMN 2M x 16 A10/AP COUNTER CELL ARRAY (BANK B) MODE Column Decoder REGISTER A0 ADDRESS BUFFER A9 A11 BA0 BA1 REFRESH COUNTER 2 ~ Row Row Row Row Decoder Decoder Decoder Decoder ~