AOZ1110 4A Synchronous EZBuck Regulator General Description Features The AOZ1110QI is a high efficiency, easy to use, 4A z 2.7V to 5.5V input voltage range synchronous buck regulator optimized for portable z 30m high-side and 20m low-side MOSFET electronic devices. The AOZ1110QI works from a 2.7V to z Efficiency up to 95% 5.5V input voltage range, and provides up to 4A of z Adjustable soft start continuous output current with an output voltage adjustable down to 0.8V. With a 1% output accuracy z Output voltage adjustable down to 0.8V rating, the AOZ1110 is designed for low tolerance z 4A continuous output current applications, such as DSPs and FPGAs. z Selectable 500kHz & 1MHz PWM operation z Cycle-by-cycle current limit The AOZ1110QI is available in a 24-pin 4X4 QFN package and is rated over a -40C to +85C ambient z Over-voltage protection temperature range. z Short-circuit protection z Thermal shutdown z Power good indicator z Small size 4x4 QFN-24 package Applications z Point of load DC/DC conversion for DSPs, FPGAs, ASICs and microprocessors z DVD and HDD z Notebook PCs z Telecom/Networking/Datacom equipment Typical Application 5V VIN C1 22F MCU R3 Ceramic VDD VIN PGOOD EN L1 1.0uH VOUT FSEL LX AOZ1110QI COMP R1 C2, C3 R C FB SS 22F AGND PGND Ceramic R2 C C Css = NC Figure 1. Typical Application Rev. 1.0 October 2010 www.aosmd.com Page 1 of 16 Not Recommended For New DesignsAOZ1110 Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ1110QI -40C to +85C 24-pin 4mm x 4mm QFN Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs compliant.jsp for additional information. Pin Configuration 24 23 22 21 20 19 1 COMP 18 LX FB 2 17 LX 3 EN 16 LX 4 PG 15 LX NC 5 14 LX 6 NC 13 LX 78 9 10 11 12 24-Pin 4mm x 4mm QFN (Top View) Pin Description Pin Number Pin Name Pin Function 1 COMP External loop compensation pin. 2 FB The FB pin is used to determine the output voltage via a resistor divider between the output and GND. 3 EN Device enable pin, active high. 4 PGOOD Power good signal output pin. It is an open drain logic output used to indicate the status of output voltages. Connect a pull up resistor to VIN. 5,6 NC No connect. 7 FSEL Frequency Selection Pin. Tie this pin to ground, to set the switching frequency to 500kHz tie this pin to VDD, to set the switching frequency to 1MHz. 8, 23 AGND Reference connection for controller circuit. All AGND pins are connected internally. Electrically needs to be connected to PGND. Also used as thermal connection for controller circuit. 9 VDD Supply voltage to control circuit and gate drivers. Connect a 10 resistor between VIN and VDD and a 0.1 F capacitor from VDD to AGND to decouple noise voltage. 10, 11, 12 VIN Supply voltage input. All VIN pins must be connected together externally. When VIN voltage rises above the UVLO threshold the device starts up. 13, 14, 15, 16, 17, LX PWM output connection to inductor. All LX pins must be connected together externally. 18, 19, 20 Also used as thermal connection for internal MOSFET. 21, 22 PGND Power ground. All PGND pins must be connected together. Electrically needs to be connected to AGND. 24 SS Soft start pin. Connect a capacitor externally to control soft start period. Leave it open for internal set soft-start time. Rev. 1.0 October 2010 www.aosmd.com Page 2 of 16 Not Recommended For New Designs FSEL SS AGND AGND VDD PGND VIN PGND VIN LX VIN LX