Low Noise, 90 MHz Variable Gain Amplifier Data Sheet AD603 The decibel gain is linear in dB, accurately calibrated, and stable FEATURES over temperature and supply. The gain is controlled at a high Linear-in-dB gain control impedance (50 M), low bias (200 nA) differential input the Pin-programmable gain ranges scaling is 25 mV/dB, requiring a gain control voltage of only 11 dB to +31 dB with 90 MHz bandwidth 1 V to span the central 40 dB of the gain range. An overrange 9 dB to 51 dB with 9 MHz bandwidth and underrange of 1 dB is provided whatever the selected range. Any intermediate range, for example 1 dB to +41 dB The gain control response time is less than 1 s for a 40 dB change. with 30 MHz bandwidth Bandwidth independent of variable gain The differential gain control interface allows the use of either 1.3 nV/Hz input noise spectral density differential or single-ended positive or negative control voltages. 0.5 dB typical gain accuracy Several of these amplifiers may be cascaded and their gain control gains offset to optimize the system SNR. The AD603 can drive a load impedance as low as 100 with APPLICATIONS low distortion. For a 500 load in shunt with 5 pF, the total RF/IF AGC amplifiers harmonic distortion for a 1 V sinusoidal output at 10 MHz is Video gain controls typically 60 dBc. The peak specified output is 2.5 V minimum A/D range extensions into a 500 load. Signal measurements The AD603 uses a patented proprietary circuit topologythe X-AMP. The X-AMP comprises a variable attenuator of 0 dB GENERAL DESCRIPTION to 42.14 dB followed by a fixed-gain amplifier. Because of the The AD603 is a low noise, voltage-controlled amplifier for use attenuator, the amplifier never has to cope with large inputs and in RF and IF AGC systems. It provides accurate, pin-selectable can use negative feedback to define its (fixed) gain and dynamic gains of 11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to performance. The attenuator has an input resistance of 100 , 51+ dB with a bandwidth of 9 MHz. Any intermediate gain laser trimmed to 3%, and comprises a 7-stage R-2R ladder range may be arranged using one external resistor. The input network, resulting in an attenuation between tap points of referred noise spectral density is only 1.3 nV/Hz, and power 6.021 dB. A proprietary interpolation technique provides a consumption is 125 mW at the recommended 5 V supplies. continuous gain control function that is linear in dB. The AD603 is specified for operation from 40C to +85C. FUNCTIONAL BLOCK DIAGRAM SCALING PRECISION PASSIVE FIXED-GAIN REFERENCE INPUT ATTENUATOR AMPLIFIER GPOS VOUT V G GNEG 6.44k* GAIN- AD603 CONTROL FDBK INTERFACE 694* 0dB 6.02dB 12.04dB 18.06dB 24.08dB 30.1dB 36.12dB 42.14dB VINP RR R R R R R 20* 2R 2R 2R 2R 2R 2R R COMM R-2R LADDER NETWORK *NOMINAL VALUES. Figure 1. Rev. K Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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All rights reserved. 00539-001AD603 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 The Gain Control Interface ....................................................... 13 Applications ....................................................................................... 1 Programming the Fixed-Gain Amplifier Using Pin St rapping ...................................................................................... 13 General Description ......................................................................... 1 Using the AD603 in Cascade ........................................................ 15 Functional Block Diagram .............................................................. 1 Sequential Mode (Optimal SNR) ............................................. 15 Revision History ............................................................................... 2 Parallel Mode (Simplest Gain Control Interface) .................. 16 Specif icat ions ..................................................................................... 3 Low Gain Ripple Mode (Minimum Gain Error) ................... 17 Absolute Maximum Ratings ............................................................ 4 Applications Information .............................................................. 18 ESD Caution .................................................................................. 4 A Low Noise AGC Amplifier .................................................... 18 Pin Configurations and Function Descriptions ........................... 5 Caution ........................................................................................ 19 Typical Performance Characteristics ............................................. 6 Evaluation Board ............................................................................ 20 Test Circuits ..................................................................................... 11 Outline Dimensions ....................................................................... 22 Theory of Operation ...................................................................... 12 Ordering Guide .......................................................................... 23 Noise Performance ..................................................................... 12 REVISION HISTORY 4/12Rev. J to Rev. K 3/05Rev. F to Rev. G Changes to Table 1 ............................................................................ 3 Updated Format .................................................................. Universal Added Figure 10 and Figure 11 Renumbered Sequentially ....... 7 Change to Features ............................................................................ 1 Added Test Circuits Section .......................................................... 11 Changes to General Description ..................................................... 1 Moved Figure 29 and Figure 30 .................................................... 11 Change to Figure 1 ............................................................................ 1 Changes to Specifications ................................................................. 3 12/11Rev. I to Rev. J New Figure 4 and Renumbering Subsequent Figures .................. 6 Changes to Figure 1 ......................................................................... 1 Change to Figure 10 .......................................................................... 7 Changes to Evaluation Board Section .......................................... 19 Change to Figure 23 .......................................................................... 9 Changes to Figure 48 Through Figure 50 .................................... 19 Change to Figure 29 ....................................................................... 12 Changes to Figure 51 Through Figure 54 .................................... 20 Updated Outline Dimensions ....................................................... 20 Added Figure 57 .............................................................................. 22 4/04Rev. E to Rev. F Changes to Specifications ................................................................. 2 5/07Rev. G to Rev. H Changes to Ordering Guide ............................................................. 3 Changes to Layout .......................................................................... 14 Changes to Layout .......................................................................... 15 8/03Rev. D to Rev E Changes to Layout .......................................................................... 16 Updated Format .................................................................. Universal Inserted Evaluation Board Section, and Figure 48 to Changes to Specifications ................................................................. 2 Figure 51 .......................................................................................... 19 Changes to TPCs 2, 3, 4 .................................................................... 4 Inserted Figure 52 and Table 4 ...................................................... 20 Changes to Sequential Mode (Optimal S/N Ratio) section ......... 9 Change to Figure 8 ......................................................................... 10 Changes to Ordering Guide .......................................................... 21 Updated Outline Dimensions ....................................................... 14 Rev. K Page 2 of 24