MCP6S26-I/SL Microchip

Resistor Ladder (R ) LAD MCP6S21/2/6/8 Single-Ended, Rail-to-Rail I/O, Low Gain PGA Features Description Multiplexed Inputs: 1, 2, 6 or 8 channels The Microchip Technology Inc. MCP6S21/2/6/8 are analog Programmable Gain Amplifiers (PGA). They 8 Gain Selections: can be configured for gains from +1 V/V to +32 V/V and - +1, +2, +4, +5, +8, +10, +16 or +32 V/V the input multiplexer can select one of up to eight chan- Serial Peripheral Interface (SPI) nels through an SPI port. The serial interface can also Rail-to-Rail Input and Output put the PGA into shutdown to conserve power. These Low Gain Error: 1% (max) PGAs are optimized for high speed, low offset voltage Low Offset: 275 V (max) and single-supply operation with rail-to-rail input and output capability. These specifications support single High Bandwidth: 2 to 12 MHz (typ) supply applications needing flexible performance or Low Noise: 10 nV/ Hz 10 kHz (typ) multiple inputs. Low Supply Current: 1.0 mA (typ) The one channel MCP6S21 and the two channel Single Supply: 2.5V to 5.5V MCP6S22 are available in 8-pin PDIP, SOIC and MSOP packages. The six channel MCP6S26 is avail- Typical Applications able in 14-pin PDIP, SOIC and TSSOP packages. The A/D Converter Driver eight channel MCP6S28 is available in 16-pin PDIP and SOIC packages. All parts are fully specified from Multiplexed Analog Applications -40C to +85C. Data Acquisition Industrial Instrumentation Block Diagram Test Equipment V DD Medical Instrumentation CH0 + Package Types CH1 V OUT CH2 - MCP6S21 MCP6S22 CH3 MUX PDIP, SOIC, MSOP PDIP, SOIC, MSOP CH4 CH5 V 1 8 V V 1 8 V OUT DD OUT DD R CH6 F CH0 2 CH0 2 7 8 7 SCK SCK CH7 Gain Switches V 3 6 SI CH1 3 6 SI REF CS R V G V 4 5 CS 4 5 CS SI SS SS SPI SO Logic SCK MCP6S26 MCP6S28 POR PDIP, SOIC, TSSOP PDIP, SOIC V V V V 1 14 1 16 V OUT DD OUT DD V REF SS CH0 2 13 SCK CH0 2 15 SCK 12 CH1 3 SO CH1 3 14 SO CH2 4 13 SI CH2 4 11 SI CH3 5 10 CS CH3 5 12 CS V V CH4 6 9 CH4 6 11 SS SS V CH5 V CH5 7 8 7 10 REF REF 8 CH6 9 CH7 2003-2012 Microchip Technology Inc. DS21117B-page 1MCP6S21/2/6/8 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function Absolute Maximum Ratings V Analog Output OUT CH0-CH7 Analog Inputs V - V .........................................................................7.0V DD SS V Negative Power Supply All inputs and outputs....................... V - 0.3V to V +0.3V SS SS DD Difference Input voltage ........................................ V - V V Positive Power Supply DD SS DD Output Short Circuit Current...................................continuous SCK SPI Clock Input Current at Input Pin 2mA SI SPI Serial Data Input Current at Output and Supply Pins 30 mA SO SPI Serial Data Output Storage temperature .....................................-65C to +150C CS SPI Chip Select Junction temperature ..................................................+150C V External Reference Pin REF ESD protection on all pins (HBM MM) 2 kV 200V Notice: Stresses above those listed underMaximum Rating may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25C, V = +2.5V to +5.5V, V = GND, V = V , G = +1 V/V, A DD SS REF SS Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R =10k to V /2, SI and SCK are tied low and CS is tied high. L DD Parameters Sym Min Typ Max Units Conditions Amplifier Input Input Offset Voltage V -275 +275 V G = +1, V = 4.0V OS DD Input Offset Voltage Drift V / T 4 V/CT = -40 to +85C OS A A Power Supply Rejection Ratio PSRR 70 85 dB G = +1 (Note 1) Input Bias Current I 1 pA CHx = V /2 B DD Input Bias Current over I 250 pA T = -40 to +85C, B A Temperature CHx = V /2 DD 13 Input Impedance Z 10 15 pF IN Input Voltage Range V V 0.3 V +0.3 V IVR SS DD Amplifier Gain Nominal Gains 1 to 32 V/V +1, +2, +4, +5, +8, +10, +16 or +32 DC Gain Error G = +1 g -0.1 +0.1 % V 0.3V to V 0.3V E OUT DD G +2 g -1.0 +1.0 % V 0.3V to V 0.3V E OUT DD DC Gain Drift G = +1 G/ T 0.0002 %/C T = -40 to +85C A A G +2 G/ T 0.0004 %/C T = -40 to +85C A A Internal Resistance R 3.4 4.9 6.4 k (Note 1) LAD Internal Resistance over R /T +0.028 %/C (Note 1) LAD A Temperature T = -40 to +85C A Amplifier Output DC Output Non-linearity G = +1 V 0.003 % of FSR V = 0.3V to V 0.3V, V = 5.0V ONL OUT DD DD G +2 V 0.001 % of FSR V = 0.3V to V 0.3V, V = 5.0V ONL OUT DD DD Maximum Output Voltage Swing V , V V +20 V -100 mV G +2 0.5V output overdrive OH OL SS DD V +60 V -60 G +2 0.5V output overdrive, SS DD V = V /2 REF DD Short-Circuit Current I 30 mA O(SC) Note 1: R (R + R in Figure 4-1) connects V , V and the inverting input of the internal amplifier. The MCP6S22 has LAD F G REF OUT V tied internally to V , so V is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We REF SS SS recommend the MCP6S22s V pin be tied directly to ground to avoid noise problems. SS 2: I includes current in R (typically 60 A at V = 0.3V). Both I and I exclude digital switching currents. Q LAD OUT Q Q SHDN 3: The output goes Hi-Z and the registers reset to their defaults see Section 5.4, Power-On Reset. DS21117B-page 2 2003-2012 Microchip Technology Inc.