AD5347BRU Analog Devices

2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs Data Sheet AD5346/AD5347/AD5348 FEATURES GENERAL DESCRIPTION 1 AD5346: octal 8-bit DAC The AD5346/AD5347/AD5348 are octal 8-, 10-, and 12-bit AD5347: octal 10-bit DAC DACs, operating from a 2.5 V to 5.5 V supply. These devices AD5348: octal 12-bit DAC incorporate an on-chip output buffer that can drive the output Low power operation: 1.4 mA (max) at 3.6 V to both supply rails, and also allow a choice of buffered or Power-down to 120 nA at 3 V, 400 nA at 5 V unbuffered reference input. Guaranteed monotonic by design over all codes CS The AD5346/AD5347/AD5348 have a parallel interface. Rail-to-rail output range: 0 V to V or 0 V to 2 V REF REF selects the device and data is loaded into the input registers on Power-on reset to 0 V WR the rising edge of . A readback feature allows the internal LDAC Simultaneous update of DAC outputs via pin DAC registers to be read back through the digital port. CLR Asynchronous facility Readback The GAIN pin on these devices allows the output range to be Buffered/unbuffered reference inputs set at 0 V to VREF or 0 V to 2 VREF. WR 20 ns time Input data to the DACs is double-buffered, allowing simultane- 38-lead TSSOP/6 mm 6 mm 40-lead LFCSP packaging ous update of multiple DACs in a system using the LDAC pin. Temperature range: 40C to +105C CLR An asynchronous input is also provided, which resets the APPLICATIONS contents of the input register and the DAC register to all zeros. Portable battery-powered instruments These devices also incorporate a power-on reset circuit that Digital gain and offset adjustment ensures that the DAC output powers on to 0 V and remains Programmable voltage and current sources there until valid data is written to the device. Optical networking All three parts are pin compatible, which allows users to select Automatic test equipment the amount of resolution appropriate for their application Mobile communications without redesigning their circuit board. Programmable attenuators Industrial process control FUNCTIONAL BLOCK DIAGRAM V V AB V CD DD AGND DGND REF REF POWER-ON AD5348 RESET BUF INPUT DAC STRING GAIN REGISTER REGISTER BUFFER V A DAC A OUT DB11 INPUT DAC . STRING . REGISTER BUFFER V B REGISTER OUT DAC B . DB0 INPUT DAC STRING BUFFER V C OUT REGISTER REGISTER DAC C INTER- CS DAC INPUT STRING V D BUFFER FACE OUT REGISTER REGISTER DAC D RD LOGIC INPUT DAC STRING V E WR REGISTER REGISTER BUFFER DAC E OUT DAC INPUT STRING A2 REGISTER BUFFER V F REGISTER OUT DAC F INPUT DAC STRING A1 BUFFER V G REGISTER REGISTER DAC G OUT A0 INPUT DAC STRING REGISTER REGISTER BUFFER V H OUT DAC H CLR POWER-DOWN LDAC LOGIC V GH V EF REF REF PD Figure 1. 1 Protected by U.S. Patent No. 5,969,657. Rev. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03331-0-001AD5346/AD5347/AD5348 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Parallel Interface ......................................................................... 17 Applications ....................................................................................... 1 Power-On Reset .......................................................................... 18 General Description ......................................................................... 1 Power-Down Mode .................................................................... 18 Functional Block Diagram .......................................................... 1 Suggested Data Bus Formats ..................................................... 19 Revision History ............................................................................... 2 Applications Information .............................................................. 20 Specif icat ions ..................................................................................... 3 Typical Application Circuits ..................................................... 20 AC Characteristics ........................................................................ 5 Bipolar Operation Using the AD5346/AD5347/AD5348 ..... 20 Timing Characteristics ................................................................ 5 Decoding Multiple AD5346/AD5347/AD5348s .................... 21 Absolute Maximum Ratings ............................................................ 7 AD5346/AD5347/AD5348 as Digitally Programmable Window Detectors ...................................................................... 21 ESD Caution .................................................................................. 7 Programmable Current Source ................................................ 21 Pin Configurations and Function Descriptions ........................... 8 Coarse and Fine Adjustment Using the Terminology .................................................................................... 11 AD5346/AD5347/AD5348 ....................................................... 22 Typical Performance Characteristics ........................................... 13 Power Supply Bypassing and Grounding ................................ 22 Functional Description .................................................................. 17 Outline Dimensions ....................................................................... 23 Digital-to-Analog Section ......................................................... 17 Ordering Guide .......................................................................... 24 Resistor String ............................................................................. 17 DAC Reference Input ................................................................. 17 Output Amplifier ........................................................................ 17 REVISION HISTORY 6/15Rev. 0 to Rev. A Changes to Figure 6 .......................................................................... 8 Changes to Figure 8 .......................................................................... 9 Changes to Figure 10 ...................................................................... 10 Deleted Driving V from the Reference Voltage Section and DD Figure 42 Renumbered Sequentially ........................................... 20 Deleted Table 9 and Table 10 Renumbered Sequentially ......... 23 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 11/03Revision 0: Initial Version Rev. A Page 2 of 24