High Speed, Precision a Sample-and-Hold Amplifier AD585 FEATURES FUNCTIONAL BLOCK DIAGRAM 3.0 ms Acquisition Time to 60.01% max Low Droop Rate: 1.0 mV/ms max DIP LCC/PLCC Package Sample/Hold Offset Step: 3 mV max Aperture Jitter: 0.5 ns Extended Temperature Range: 558C to +1258C Internal Hold Capacitor Internal Application Resistors 612 V or 615 V Operation Available in Surface Mount APPLICATIONS Data Acquisition Systems Data Distribution Systems Analog Delay & Storage Peak Amplitude Measurements MIL-STD-883 Compliant Versions Available The AD585 is available in three performance grades. The JP PRODUCT DESCRIPTION grade is specified for the 0C to +70C commercial temperature The AD585 is a complete monolithic sample-and-hold circuit range and packaged in a 20-pin PLCC. The AQ grade is speci- consisting of a high performance operational amplifier in series fied for the 25C to +85C industrial temperature range and is with an ultralow leakage analog switch and a FET input inte- packaged in a 14-pin cerdip. The SQ and SE grades are speci- grating amplifier. An internal holding capacitor and matched fied for the 55C to +125C military temperature range and applications resistors have been provided for high precision and are packaged in a 14-pin cerdip and 20-pin LCC. applications flexibility. The performance of the AD585 makes it ideal for high speed PRODUCT HIGHLIGHTS 10- and 12-bit data acquisition systems, where fast acquisition 1. The fast acquisition time (3 s) and low aperture jitter time, low sample-to-hold offset, and low droop are critical. The (0.5 ns) make it the first choice for very high speed data AD585 can acquire a signal to 0.01% in 3 s maximum, and acquisition systems. then hold that signal with a maximum sample-to-hold offset of 2. The droop rate is only 1.0 mV/ms so that it may be used in 3 mV and less than 1 mV/ms droop, using the on-chip hold slower high accuracy systems without the loss of accuracy. capacitor. If lower droop is required, it is possible to add a 3. The low charge transfer of the analog switch keeps sample-to larger external hold capacitor. hold offset below 3 mV with the on-chip 100 pF hold capaci- The high speed analog switch used in the AD585 exhibits tor, eliminating the trade-off between acquisition time and aperture jitter of 0.5 ns, enabling the device to sample full scale S/H offset required with other SHAs. (20 V peak-to-peak) signals at frequencies up to 78 kHz with 4. The AD585 has internal pretrimmed application resistors for 12-bit precision. applications versatility. The AD585 can be used with any user-defined feedback net- 5. The AD585 is complete with an internal hold capacitor for work to provide any desired gain in the sample mode. On-chip ease of use. Capacitance can be added externally to reduce precision thin-film resistors can be used to provide gains of +1, the droop rate when long hold times and high accuracy are 1, or +2. Output impedance in the hold mode is sufficiently required. low to maintain an accurate output signal even when driving the dynamic load presented by a successive-approximation A/D 6. The AD585 is recommended for use with 10- and 12-bit converter. However, the output is protected against damage successive-approximation A/D converters such as AD573, from accidental short circuits. AD574A, AD674A, AD7572 and AD7672. The control signal for the HOLD command can be either active 7. The AD585 is available in versions compliant with MIL-STD- high or active low. The differential HOLD signal is compatible 883. Refer to the Analog Devices Military Products Databook with all logic families, if a suitable reference level is provided. An or current AD585/883B data sheet for detailed specifications. on-chip TTL reference level is provided for TTL compatibility. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703(typical +258C and V = 612 V or 615 V, and C = Internal, A = +1, S H AD585SPECIFICATIONS HOLD active unless otherwise noted) Model AD585J AD585A AD585S Min Typ Max Min Typ Max Min Typ Max Units SAMPLE/HOLD CHARACTERISTICS Acquisition Time, 10 V Step to 0.01% 333 s 20 V Step to 0.01% 5 5 5 s Aperture Time, 20 V p-p Input, HOLD 0 V 353535 ns Aperture Jitter, 20 V p-p Input, HOLD 0 V 0.5 0.5 0.5 ns Settling Time, 20 V p-p Input, HOLD 0 V, to 0.01% 0.5 0.5 0.5 s Droop Rate 111 mV/ms Droop Rate T to T Doubles Every 10C Double Every 10C Doubles Every 10C MIN MAX Charge Transfer 0.3 0.3 0.3 pC Sample-to-Hold Offset 3 3 3 3 3 3 mV Feedthrough 20 V p-p, 10 kHz Input 0.5 0.5 0.5 mV 1 TRANSFER CHARACTERISTICS Open Loop Gain V = 20 V p-p, R = 2k 200,000 200,000 200,000 V/V OUT L Application Resistor Mismatch 0.3 0.3 0.3 % Common-Mode Rejection V = 10 V 80 80 80 dB CM Small Signal Gain Bandwidth V = 100 mV p-p 2.0 2.0 2.0 MHz OUT Full Power Bandwidth V = 20 V p-p 160 160 160 kHz OUT Slew Rate V = 20 V p-p 10 10 10 V/s OUT Output Resistance (Sample Mode) I = 10 mA 0.05 0.05 0.05 OUT Output Short Circuit Current 50 50 50 mA Output Short Circuit Duration Indefinite Indefinite Indefinite ANALOG INPUT CHARACTERISTICS Offset Voltage 522 mV Offset Voltage, T to T 63 3 mV MIN MAX Bias Current 222 nA 2 Bias Current, T to T 55 20 50 nA MIN MAX Input Capacitance, f = 1 MHz 10 10 10 pF Input Resistance, Sample or Hold 12 12 12 20 V p-p Input, A = +1 10 10 10 DIGITAL INPUT CHARACTERISTICS TTL Reference Output 1.2 1.4 1.6 1.2 1.4 1.6 1.2 1.4 1.6 V Logic Input High Voltage T to T 2.0 2.0 2.0 V MIN MAX Logic Input Low Voltage T to T 0.8 0.8 0.7 V MIN MAX Logic Input Current (Either Input) 50 50 50 A POWER SUPPLY CHARACTERISTICS Operating Voltage Range +5, 10.8 18 +5, 10.8 18 +5, 10.8 18 V Supply Current, R = 6106 10610 mA L Power Supply Rejection, Sample Mode 70 70 70 dB TEMPERATURE RANGE Specified Performance 0 +70 25 +85 55 +125 C 3, 4 PACKAGE OPTIONS Cerdip (Q-14) AD585AQ AD585SQ LCC (E-20A) AD585SE PLCC (P-20A) AD585JP NOTES Specifications subject to change without notice. 1 Maximum input signal is the minimum supply minus a headroom voltage of 2.5 V. 2 Specifications shown in boldface are tested on all production units at final electrical Not tested at 55C. test. Results from those tests are used to calculate outgoing quality levels. 3 E = Leadless Ceramic Chip Carrier P = Plastic Leaded Chip Carrier Q = Cerdip. All min and max specifications are guaranteed, although only those shown in 4 For AD585/883B specifications, refer to Analog Devices Military Products Databook. boldface are tested on all production units. 2 REV. A