385 MHz BW IF Diversity Receiver Data Sheet AD6674 FEATURES APPLICATIONS JESD204B (Subclass 1) coded serial digital outputs Diversity multiband, multimode digital receivers In band SFDR = 83 dBFS at 340 MHz (750 MSPS) 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A In band SNR = 66.7 dBFS at 340 MHz (750 MSPS) DOCSIS 3.0 CMTS upstream receive paths 1.4 W total power per channel at 750 MSPS (default settings) HFC digital reverse path receivers Noise density = 153 dBFS/Hz at 750 MSPS GENERAL DESCRIPTION 1.25 V, 2.5 V, and 3.3 V dc supply operation The AD6674 is a 385 MHz bandwidth mixed-signal Flexible input range intermediate frequency (IF) receiver. It consists of two, 14-bit AD6674-750 and AD6674-1000 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) (ADC) and various digital signal processing blocks consisting of AD6674-500 four wideband DDCs, an NSR, and VDR monitoring. It has an 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) on-chip buffer and a sample-and-hold circuit designed for low 95 dB channel isolation/crosstalk power, small size, and ease of use. This product is designed to Amplitude detect bits for efficient automatic gain control support communications applications capable of sampling wide (AGC) implementation bandwidth analog signals of up to 2 GHz. The AD6674 is Noise shaping requantizer (NSR) option for main receiver optimized for wide input bandwidth, high sampling rate, function excellent linearity, and low power in a small package. Variable dynamic range (VDR) option for digital predistortion (DPD) function The dual ADC cores feature a multistage, differential pipelined 2 integrated wideband digital processors per channel architecture with integrated output error correction logic. Each 12-bit numerically controlled oscillator (NCO), up to ADC features wide bandwidth inputs supporting a variety of 4 cascaded half-band filters user-selectable input ranges. An integrated voltage reference Differential clock inputs eases design considerations. Integer clock divide by 1, 2, 4, or 8 Energy saving power-down modes Flexible JESD204B lane configurations Small signal dither FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1 SR DVDD DRVDD SPIVDD (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.7V TO 3.4V) BUFFER SIGNAL PROCESSING VIN+A ADC VINA DIGITAL DOWN CONVERSION DIGITAL DOWN CONVERSION DIGITAL DOWN CONVERSION DIGITAL DOWN(C4)ONVERSION (4) (4) FD A (4) 4 SERDOUT0 SIGNAL SERDOUT1 NOISE SHAPING REQUANTIZER MONITOR SERDOUT2 NOISE SHAPING REQUANTIZER (2) SERDOUT3 (2) FD B VARIABLE DYNAMIC RANGE VARIABLE DYNAMIC RANGE VIN+B ADC (2) (2) VINB BUFFER FAST DETECT V 1P0 JESD204B CLOCK SUBCLASS 1 SIGNAL GENERATION CONTROL MONITOR PDWN/ CLK+ STBY SPI CONTROL CLK 2 AD6674 4 8 AGND SYSREF SYNCINB SDIO SCLK CSB DGND DRGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com FAST DETECT DATA ROUTER MUX JESD204B HIGH SPEED SERIALIZER TX OUTPUTS 12400-001AD6674 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Numerically Controlled Oscillator .......................................... 48 Applications ....................................................................................... 1 FIR Filters ........................................................................................ 50 General Description ......................................................................... 1 General Description ................................................................... 50 Functional Block Diagram .............................................................. 1 Half-Band Filters ........................................................................ 51 Revision History ............................................................................... 3 DDC Gain Stage ......................................................................... 52 Product Highlights ........................................................................... 4 DDC Complex to Real Conversion ......................................... 52 Specifications ..................................................................................... 5 DDC Example Configurations ................................................. 53 DC Specifications ......................................................................... 5 Noise Shaping Requantizer (NSR) ............................................... 57 AC Specifications .......................................................................... 6 Decimating Half-Band Filter .................................................... 57 Digital Specifications ................................................................... 8 NSR Overview ............................................................................ 57 Switching Specifications .............................................................. 9 Variable Dynamic Range (VDR) .................................................. 60 Timing Specifications .................................................................. 9 VDR Real Mode.......................................................................... 61 Absolute Maximum Ratings .......................................................... 11 VDR Complex Mode ................................................................. 61 Thermal Characteristics ............................................................ 11 Digital Outputs ............................................................................... 63 ESD Caution ................................................................................ 11 Introduction to JESD204B Interface ........................................ 63 Pin Configuration and Function Descriptions ........................... 12 JESD204B Overview .................................................................. 63 Typical Performance Characteristics ........................................... 14 Functional Overview ................................................................. 64 AD6674-1000 .............................................................................. 14 JESD204B Link Establishment ................................................. 64 AD6674-750 ................................................................................ 18 Physical Layer (Driver) Outputs .............................................. 66 AD6674-500 ................................................................................ 22 JESD204B Tx Converter Mapping ........................................... 68 Equivalent Circuits ......................................................................... 26 Configuring the JESD204B Link .............................................. 68 Theory of Operation ...................................................................... 28 Multichip Synchronization ............................................................ 72 ADC Architecture ...................................................................... 28 SYSREF Setup/Hold Window Monitor ................................. 74 Analog Input Considerations .................................................... 28 Test Modes ....................................................................................... 76 Voltage Reference ....................................................................... 33 ADC Test Modes ........................................................................ 76 Clock Input Considerations ...................................................... 34 JESD204B Block Test Modes .................................................... 76 Power-Down/Standby Mode..................................................... 35 Serial Port Interface (SPI) .............................................................. 79 Temperature Diode .................................................................... 36 Configuration Using the SPI ..................................................... 79 ADC Overrange and Fast Detect .................................................. 37 Hardware Interface ..................................................................... 79 ADC Overrange (OR) ................................................................ 37 SPI Accessible Features .............................................................. 79 Fast Threshold Detection (FD A and FD B) ........................ 37 Memory Map .................................................................................. 80 Signal Monitor ................................................................................ 38 Reading the Memory Map Register Table ............................... 80 SPORT over JESD204B .............................................................. 38 Memory Map Register Table ..................................................... 81 Digital Downconverter (DDC) ..................................................... 41 Applications Information .............................................................. 95 DDC I/Q Input Selection .......................................................... 41 Power Supply Recommendations ............................................. 95 DDC I/Q Output Selection ....................................................... 41 Exposed Pad Thermal Heat Slug Recommendations ............ 95 DDC General Description ........................................................ 41 AVDD1 SR (Pin 57) and AGND (Pin 56, Pin 60) ................ 95 Frequency Translation ................................................................... 47 Outline Dimensions ....................................................................... 96 General Description ................................................................... 47 Ordering Guide .......................................................................... 96 DDC NCO + Mixer Loss and SFDR ........................................ 48 Rev. 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