135 MHz BW IF Diversity Receiver Data Sheet AD6679 FEATURES APPLICATIONS Parallel LVDS (DDR) outputs Diversity multiband, multimode digital receivers In-band SFDR = 82 dBFS at 340 MHz (500 MSPS) 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS) DOCSIS 3.0 CMTS upstream receive paths 1.1 W total power per channel at 500 MSPS (default settings) HFC digital reverse path receivers Noise density = 153 dBFS/Hz at 500 MSPS GENERAL DESCRIPTION 1.25 V, 2.50 V, and 3.3 V dc supply operation The AD6679 is a 135 MHz bandwidth mixed-signal intermediate Flexible input range frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) analog-to-digital converters (ADCs) and various digital signal 95 dB channel isolation/crosstalk processing blocks consisting of four wideband DDCs, an NSR, Amplitude detect bits for efficient automatic gain control and VDR monitoring. It has an on-chip buffer and a sample-and- (AGC) implementation hold circuit designed for low power, small size, and ease of use. Noise shaping requantizer (NSR) option for main receiver This product is designed to support communications applications function capable of sampling wide bandwidth analog signals of up to 2 GHz. Variable dynamic range (VDR) option for digital The AD6679 is optimized for wide input bandwidth, high sampling predistortion (DPD) function rates, excellent linearity, and low power in a small package. 2 integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO), up to The dual ADC cores feature a multistage, differential pipelined 4 cascaded half-band filters architecture with integrated output error correction logic. Each Differential clock inputs ADC features wide bandwidth inputs supporting a variety of Integer clock divide by 1, 2, 4, or 8 user-selectable input ranges. An integrated voltage reference Energy saving power-down modes eases design considerations. Small signal dither FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 DVDD DRVDD SPIVDD (1.25V) (2.50V) (3.3V) (1.25V) (1.25V) (1.22V TO 3.4V) BUFFER VIN+A D0 SIGNAL PROCESSING ADC D1 D2 VINA D3 DIGITAL DOWN- D4 CONVERSION D5 FD A (4) 16 D6 D7 FAST SIGNAL LVDS D8 DETECT MONITOR DATA LVDS OUTPUT D9 ROUTER NOISE SHAPING FD B OUTPUTS STAGING D10 MUX REQUANTIZER D11 (2) D12 V 1P0 D13 DCO BUFFER VARIABLE STATUS DYNAMIC RANGE VIN+B (2) ADC VINB FAST CLOCK DETECT CLK+ GENERATION AND ADJUST AD6679 CLK 2 SIGNAL PDWN/STBY SPI CONTROL 4 MONITOR 8 AGND SYNC SDIO SCLK CSB DGND DRGND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 13059-001AD6679 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 General Description ................................................................... 46 Applications ....................................................................................... 1 DDC NCO Plus Mixer Loss and SFDR ................................... 47 General Description ......................................................................... 1 Numerically Controlled Oscillator .......................................... 47 Functional Block Diagram .............................................................. 1 FIR Filters ........................................................................................ 49 Revision History ............................................................................... 3 Overview ..................................................................................... 49 Product Highlights ........................................................................... 4 Half-Band Filters ........................................................................ 49 Specifications ..................................................................................... 5 DDC Gain Stage ......................................................................... 51 DC Specifications ......................................................................... 5 DDC Complex to Real Conversion ......................................... 51 AC Specifications .......................................................................... 6 DDC Example Configurations ................................................. 52 Digital Specifications ................................................................... 7 Noise Shaping Requantizer (NSR) ............................................... 56 Switching Specifications .............................................................. 8 Decimating Half-Band Filter .................................................... 56 Timing Specifications .................................................................. 9 NSR Overview ............................................................................ 56 Absolute Maximum Ratings .......................................................... 18 Variable Dynamic Range (VDR) .................................................. 59 Thermal Characteristics ............................................................ 18 VDR Real Mode.......................................................................... 60 ESD Caution ................................................................................ 18 VDR Complex Mode ................................................................. 60 Pin Configurations and Function Descriptions ......................... 19 Digital Outputs ............................................................................... 62 Typical Performance Characteristics ........................................... 25 Timing.......................................................................................... 62 Equivalent Circuits ......................................................................... 28 Data Clock Output ..................................................................... 62 Theory of Operation ...................................................................... 30 ADC Overrange .......................................................................... 62 ADC Architecture ...................................................................... 30 Multichip Synchronization ............................................................ 64 Analog Input Considerations .................................................... 30 SYNC Setup and Hold Window Monitor ............................. 65 Voltage Reference ....................................................................... 32 Test Modes ....................................................................................... 67 Clock Input Considerations ...................................................... 33 ADC Test Modes ........................................................................ 67 Power-Down/Standby Mode..................................................... 35 Serial Port Interface (SPI) .............................................................. 68 Temperature Diode .................................................................... 35 Configuration Using the SPI ..................................................... 68 Virtual Converter Mapping ........................................................... 36 Hardware Interface ..................................................................... 68 ADC Overrange and Fast Detect .................................................. 38 SPI Accessible Features .............................................................. 68 ADC Overrange (OR) ................................................................ 38 Memory Map .................................................................................. 69 Fast Threshold Detection (FD A and FD B) ........................ 38 Reading the Memory Map Register Table ............................... 69 Signal Monitor ................................................................................ 39 Memory Map Register Table ..................................................... 70 Digital Downconverter (DDC) ..................................................... 40 Applications Information .............................................................. 80 DDC I/Q Input Selection .......................................................... 40 Power Supply Recommendations ............................................. 80 DDC I/Q Output Selection ....................................................... 40 Outline Dimensions ....................................................................... 81 DDC General Description ........................................................ 40 Ordering Guide .......................................................................... 81 Frequency Translation ................................................................... 46 Rev. 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