8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW Data Sheet AD7761 FEATURES Linear phase digital filter Low latency sinc5 filter Precision ac and dc performance Wideband brick wall filter: 0.005 dB ripple to 102.4 kHz 8-channel simultaneous sampling Analog input precharge buffers 256 kSPS ADC ODR per channel Power supply 97.7 dB dynamic range AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V 110.8 kHz input bandwidth (3 dB BW) IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V 120 dB THD, typical 64-lead LQFP package, no exposed pad 1 LSB INL, 1 LSB offset error, 5 LSB gain error Temperature range: 40C to +105C Optimized power dissipation vs. noise vs. input bandwidth Selectable power, speed, and input bandwidth APPLICATIONS Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel Data acquisition systems: USB/PXI/Ethernet Median (half speed): 55.4 kHz BW, 27.5 mW per channel Instrumentation and industrial control loops Low power (lowest power): 13.8 kHz BW, 9.375 mW per Audio testing and measurement channel Vibration and asset condition monitoring Input BW range: dc to 110.8 kHz 3-phase power quality analysis Programmable input bandwidth/sampling rates Sonar CRC error checking on data interface High precision medical electroencephalogram (EEG)/ Daisy-chaining electromyography (EMG)/electrocardiogram (ECG) FUNCTIONAL BLOCK DIAGRAM AVDD1A, AVDD2A, REGCAPA, AVDD1B REFx+ REFx AVDD2B REGCAPB DGND IOVDD DREGCAP BUFFERED VCM PRECHARGE 1.8V 1.8V LDO LDO VCM VCM 8 REFERENCE BUFFERS SYNC IN SYNC OUT START AIN0+ P OFFSET, - RESET CH 0 DIGITAL GAIN PHASE ADC FILTER CORRECTION AIN0 P FORMAT1 ENGINE FORMAT0 AIN1+ P OFFSET, - CH 1 GAIN PHASE ADC ADC AIN1 P CORRECTION OUTPUT DRDY SINC5 DATA LOW LATENCY AIN2+ P SERIAL DCLK OFFSET, - FILTER CH 2 INTERFACE GAIN PHASE ADC DOUT0 AIN2 P CORRECTION DOUT1 DOUT2 AIN3+ P OFFSET, - DOUT3 CH 3 GAIN PHASE ADC AIN3 P CORRECTION DOUT4 DOUT5 WIDEBAND AIN4+ P LOW RIPPLE OFFSET, DOUT6 - CH 4 FILTER GAIN PHASE ADC DOUT7 AIN4 P CORRECTION AIN5+ P OFFSET, - CH 5 GAIN PHASE ADC AIN5 ST0/CS CORRECTION P SPI ST1/SCLK CONTROL INTERFACE AIN6+ P DEC0/SDO OFFSET, - CH 6 GAIN PHASE DEC1/SDI ADC AIN6 P CORRECTION AIN7+ P OFFSET, - CH 7 PIN/SPI GAIN PHASE ADC CORRECTION P AIN7 16 ANALOG INPUT PRECHARGE BUFFERS (P) AD7761 AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3 FILTER/GPIO4 TO MODE0/GPIO0 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 14285-001AD7761 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Setting the Format of Data Output .......................................... 49 Applications ....................................................................................... 1 ADC Conversion Output: Header and Data .......................... 50 Functional Block Diagram .............................................................. 1 Functionality ................................................................................... 59 Revision History ............................................................................... 3 GPIO Functionality .................................................................... 59 General Description ......................................................................... 4 Register Map Details (SPI Control) ............................................. 60 Specifications ..................................................................................... 5 Register Map ............................................................................... 60 Timing Specifications ................................................................ 10 Channel Standby Register ......................................................... 62 1.8 V IOVDD Timing Specifications ....................................... 11 Channel Mode A Register ......................................................... 63 Absolute Maximum Ratings .......................................................... 15 Channel Mode B Register ......................................................... 63 Thermal Resistance .................................................................... 15 Channel Mode Select Register .................................................. 64 ESD Caution ................................................................................ 15 Power Mode Select Register ...................................................... 64 Pin Configuration and Function Descriptions ........................... 16 General Device Configuration Register .................................. 65 Typical Performance Characteristics ........................................... 20 Data Control: Soft Reset, Sync, and Single-Shot Control Register ........................................................................................ 66 Terminology .................................................................................... 26 Interface Configuration Register .............................................. 66 Theory of Operation ...................................................................... 27 Digital Filter RAM Built in Self Test (BIST) Register ............ 67 Clocking, Sampling Tree, and Power Scaling ............................. 27 Status Register ............................................................................. 67 Noise Performance and Resolution .......................................... 28 Revision Identification Register ............................................... 68 Applications Information .............................................................. 30 GPIO Control Register .............................................................. 68 Power Supplies ............................................................................ 31 GPIO Write Data Register ......................................................... 69 Device Configuration ................................................................ 32 GPIO Read Data Register .......................................................... 69 Pin Control Mode ....................................................................... 32 Analog Input Precharge Buffer Enable Register Channel 0 to SPI Control .................................................................................. 35 Channel 3 .................................................................................... 69 SPI Control Functionality ......................................................... 36 Analog Input Precharge Buffer Enable Register Channel 4 to SPI Control Mode Extra Diagnostic Features ........................ 38 Channel 7 .................................................................................... 70 Circuit Information ........................................................................ 39 Positive Reference Precharge Buffer Enable Register ............ 70 Core Signal Chain ....................................................................... 39 Negative Reference Precharge Buffer Enable Register .......... 71 Analog Inputs .............................................................................. 40 Offset Registers ........................................................................... 71 VCM ............................................................................................. 41 Gain Registers ............................................................................. 72 Reference Input ........................................................................... 42 Sync Phase Offset Registers ...................................................... 72 Clock Selection ........................................................................... 42 ADC Diagnostic Receive Select Register ................................ 72 Digital Filtering ........................................................................... 42 ADC Diagnostic Control Register ........................................... 73 Decimation Rate Control .......................................................... 46 Modulator Delay Control Register ........................................... 74 Antialiasing ................................................................................. 46 Chopping Control Register ....................................................... 74 Calibration ................................................................................... 48 Outline Dimensions ....................................................................... 75 Data Interface .................................................................................. 49 Ordering Guide .......................................................................... 75 Rev. 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