6.5 Gbps Quad Buffer Mux/Demux AD8158 FEATURES FUNCTIONAL BLOCK DIAGRAM Quad 2:1 mux/1:2 demux TRANSMIT RECEIVE PRE- Optimized for dc to 6.5 Gbps NRZ data EQUALIZATION EMPHASIS Per-lane P/N pair inversion for routing ease Ix A 3:0 EQ Programmable input equalization 2:1 Ox C 3:0 Compensates up to 40 inches of FR4 Ix B 3:0 EQ Loss-of-signal detection Programmable output pre-emphasis up to 12 dB Programmable output levels with squelch and disable Ox A 3:0 Accepts ac-coupled or dc-coupled differential CML inputs 1:2 EQ Ix C 3:0 50 on-chip termination Ox B 3:0 1:2 demux supports unicast or bicast operation TRANSMIT QUAD RECEIVE PRE- 2:1 EQUALIZATION Port-level loopback EMPHASIS MULTIPLEXER/ 1:2 Port or single lane switching DEMULTIPLEXER 1.8 V to 3.3 V flexible core supply LB A User-settable I/O supply from V to 1.2 V CC LB B LB C Low power, typically 2.0 W in basic configuration PE A 100-lead LFCSP PE B SCL PE C SDA 40C to +85C operating temperature range 2 I C EQ A 1:0 I2C A0 TOGGLE CONTROL CONTROL EQ B 1:0 I2C A1 LOGIC LOGIC EQ C 1:0 APPLICATIONS I2C A2 SEL 3:0 BICAST Low cost redundancy switch SEL4G SONET OC48/SDH16 and lower data rates RESETb LOS INT XAUI/GbE/FC/Infiniband over backplane AD8158 OIF CEI 6.25 Gbps over backplane Serial data-level shift Figure 1. 4-/8-/12-lane equalizers or redrivers GENERAL DESCRIPTION The AD8158 is an asynchronous, protocol-agnostic, quad-lane The main application of the AD8158 is to support redundancy 2:1 switch with a total of 12 differential CML inputs and on both the backplane and the line interface sides of a serial 12 differential CML outputs. The signal path supports NRZ link. The demultiplexing path implements unicast and bicast signaling with data rates up to 6.5 Gbps per lane. Each lane capability, allowing the part to support either 1 + 1 or 1:1 offers programmable receive equalization, programmable redundancy. output pre-emphasis, programmable output levels, and loss-of- The AD8158 is also suited for testing high speed serial links signal detection. because of its ability to duplicate incoming data. In a port- The nonblocking switch-core of the AD8158 implements a monitoring application, the AD8158 can maintain link- 2:1 multiplexer and 1:2 demultiplexer per lane and supports connectivity with a pass-through connection from Port C to independent lane switching through the four select pins, Port A while sending a duplicate copy of the data to test SEL 3:0 . Each port is a four-lane link. Every lane implements equipment on Port B. an asynchronous path supporting dc to 6.5 Gbps NRZ data, The rich feature set of the AD8158 can be controlled either fully independent of other lanes. The AD8158 has low latency through external toggle pins or by setting on-chip control and very low lane-to-lane skew. 2 registers through the I C interface. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06646-001AD8158 TABLE OF CONTENTS Features .............................................................................................. 1 AD8158 Power Consumption .................................................. 23 2 Applications ....................................................................................... 1 I C Control Interface ...................................................................... 25 Functional Block Diagram .............................................................. 1 Serial Interface General Functionality..................................... 25 2 General Description ......................................................................... 1 I C Interface Data Transfers: Data Write ................................ 25 2 Revision History ............................................................................... 2 I C Interface Data Transfers: Data Read ................................. 26 Specif icat ions ..................................................................................... 3 Applications Information .............................................................. 27 2 I C Timing Specifications ............................................................ 5 Output Compliance ................................................................... 28 Absolute Maximum Ratings ............................................................ 6 Signal Levels and Common-Mode Shift for AC-Coupled and DC-Coupled Outputs ................................................................ 29 ESD Caution .................................................................................. 6 Supply Sequencing ..................................................................... 31 Pin Configuration and Function Descriptions ............................. 7 Reset ............................................................................................. 31 Typical Performance Characteristics ........................................... 10 Single Supply vs. Multiple Supply Operation ......................... 31 Theory of Operation ...................................................................... 16 Printed Circuit Board (PCB) Layout Guidelines ................... 32 The Switch (Mux/Demux/Unicast/Bicast/Loopback) ........... 17 Register Map ................................................................................... 34 Receivers ...................................................................................... 19 Outline Dimensions ....................................................................... 36 Loss of Signal (LOS) ................................................................... 21 Ordering Guide .......................................................................... 36 Transmitters ................................................................................ 22 REVISION HISTORY 12/09Rev. A: Rev. B Changes to LOS to Output Squelch Parameter (Table 1) ............ 3 Added Endnote 1 to Table 2 ............................................................ 5 Added Speed Select (SEL4G) to Table 6 ...................................... 17 Changes to Loss of Signal (LOS) section ..................................... 21 Deleted Table 15 .............................................................................. 21 Changes to Serial Interface General Functionality Section ...... 25 Added Reset Section ....................................................................... 31 Changes to Table 22 ........................................................................ 34 9/09Rev. 0: Rev. A Reorganized Layout ............................................................ Universal Changes to Specifications Section .................................................. 3 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Theory of Operation Section .................................... 16 Added Table 15 Renumbered Sequentially ................................ 21 Changes to Applications Information Section ............................ 27 Changes to Table 23 ........................................................................ 34 6/08Revision 0: Initial Version Rev. B Page 2 of 36