Precision Edge ULTRA-LOW JITTER DUAL 2 2 Micrel, Inc. SY58024U Precision Edge CROSSPOINT SWITCH w/ CML OUTPUTS SY58024U AND INTERNAL I/O TERMINATION FEATURES Guaranteed AC performance over temperature and voltage: Precision Edge >10.7Gbps data throughput DESCRIPTION <60ps t /t times r f <350ps t (IN-to-Q) pd The SY58024U is a 2.5V/3.3V precision, high-speed, fully <20ps skew differential dual CML crosspoint switch. The SY58024U is Low jitter: optimized to provide two identical output copies with less than 20ps of skew and ultra-low jitter. The SY58024U can <10ps total jitter (clock) PP process clock signals as fast as 6GHz or data patterns up <1ps random jitter (data) RMS to 10.7Gbps. <10ps deterministic jitter (data) PP The differential input includes Micrels unique, 3-pin input Crosstalk induced jitter: <0.7ps RMS termination architecture that allows the SY58024U to directly Unique, patent-pending input isolation minimizes interface to LVPECL, LVDS, and CML differential signal adjacent channel crosstalk (AC- or DC-coupled) without any level-shifting or termination resistor networks in the signal path. The CML outputs Accepts an input signal as low as 100mV features a 400mV typical swing into 50 loads, and provides Unique, patent-pending input termination and VT pin an extremely fast rise/fall time guaranteed to be less than accepts DC-coupled and AC-coupled differential 60ps. inputs: LVPECL, LVDS, and CML The SY58024U operates from a 2.5V 5% supply or Fully differential inputs/outputs 3.3V 10% supply and is guaranteed over the full industrial 50 source terminated CML outputs temperature range (40C to +85C). For applications that Power supply 2.5V 5% and 3.3V 10% require high-speed single channel CML switches, consider the SY58023U. The SY58024U is part of Micrels high- Industrial 40C to +85C temperature range speed, Precision Edge product line. Available in 32-pin (5mm 5mm) MLF package Datasheets and support documentation can be found on Micrels website at: www.micrel.com. APPLICATIONS Gigabit Ethernet data/clock routing SONET data/clocking routing Switch fabric clock routing Redundant switchover Backplane redundancy Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Rev.: I Amendment: /0 M9999-082807 1 Issue Date: August 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY58024U PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish 1 24 INB1 GND SY58024UMI MLF-32 Industrial SY58024U Sn-Pb 23 VCC VTB1 2 /INB1 3 22 QA0 (2) SY58024UMITR MLF-32 Industrial SY58024U Sn-Pb 4 21 SELB0 /QA0 (3) SY58024UMG MLF-32 Industrial SY58024U with Pb-Free INB0 5 20 VCC 6 19 VTB0 QA1 Pb-Free bar-line indicator NiPdAu 7 18 /INB0 /QA1 (2, 3) SELB1 8 VCC SY58024UMGTR MLF-32 Industrial SY58024U with Pb-Free 17 910 11 1213141516 Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF (MLF-32) 3. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 25, 27 INA0, /INA0, Differential Signal: Each pin of this pair internally terminates with 50 to the VT pin. The 29, 31, INA1, /INA1, input will default to an indeterminate state if left open. See Input Interface Application 1, 3, INB1, /INB1 section. 5, 7 INB0, /INB0 26, 30 VTA0, VTA1, Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a 2, 6 VTB1, VTB0 center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See Input Interface Application section. 32, 28, SELA0, SELA1, Select Input: TTL/CMOS select input controls that selects inputs IN0, or IN1, for their 8, 4 SELB1, SELB0 respective banks A and B. Each input is internally connected to a 25k pull-up resistor and will default to a logic high state if left open. 9,24 GND, Ground. Exposed pad must be connected to a ground plane that is the same potential as the Exposed Pad device ground pins. 10,13,16, VCC Positive Power Supply: Bypass with 0.1F0.01F low ESR capacitors as close to the V CC 17, 20, 23 pins as possible. 11, 12, /QB0, QB0, CML Differential Output Pairs: Differential buffered output copy of the selected input signal. 15, 14 /QB1, QB1, The CML single-ended output swing is typically 400mV into 50 or 100 across the pair. 18, 19, /QA1, QA1, Unused output pairs may be left floating with no impact on jitter. See CML Output 21, 22 /QA0, QA0 Termination section. TRUTH TABLE SELA0 SELA1 QA0 QA1 SELB0 SELB1 QB0 QB1 00 INA0 INA0 0 0 INB0 INB0 01 INA0 INA1 0 1 INB1 INB1 10 INA1 INA0 1 0 INB1 INB0 11 INA1 INA1 1 1 INB1 INB1 M9999-082807 2 hbwhelp micrel.com or (408) 955-1690 SELA0 GND VCC /INA1 /QB0 VTA1 QB0 INA1 VCC SELA1 QB1 /INA0 /QB1 VTA0 INA0 VCC