Low Cost, 225 MHz, 16 16 Crosspoint Switches Data Sheet AD8114/AD8115 FEATURES FUNCTIONAL BLOCK DIAGRAM SER/PAR D0 D1 D2 D3 D4 16 16 high speed nonblocking switch arrays A0 AD8114 G = 1 A1 AD8115 G = 2 A2 CLK A3 Serial or parallel programming of switch array 80-BIT SHIFT REGISTER Serial data out allows daisy-chaining of multiple DATA WITH 5-BIT DATA IN OUT PARALLEL LOADING 16 16 arrays to create larger switch arrays UPDATE 80 High impedance output disable allows connection of SET INDIVIDUAL CE PARALLEL LATCH multiple devices without loading the output bus OR RESET ALL OUTPUTS RESET For smaller arrays see the AD8108/AD8109 (8 8) or TOOF 80 16 AD8110/AD8111 (16 8) switch arrays DECODE 16 5:16 DECODERS Complete solution OUTPUT Buffered inputs AD8114/AD8115 BUFFER 256 G = +1, Programmable high impedance outputs G = +2 16 output amplifiers, AD8114 (G = 1), AD8115 (G = 2) Drives 150 loads Excellent video performance 25 MHz, 0.1 dB gain flatness SWITCH MATRIX 0.05%/0.05 differential gain/differential phase error 16 16 INPUTS OUTPUTS (R = 150 ) L Excellent ac performance 3 dB bandwidth: 225 MHz Slew rate: 375 V/s Low power of 700 mW (2.75 mW per point) Low all hostile crosstalk of 70 dB at 5 MHz Figure 1. Reset pin allows disabling of all outputs (connected through a capacitor to ground provides power-on reset capability) The differential gain and differential phase of better than 0.05% 100-lead LQFP (14 mm 14 mm) and 0.05, respectively, along with a 0.1 dB flatness out to 25 MHz while driving a 75 back-terminated load, make the AD8114/ APPLICATIONS AD8115 ideal for all types of signal switching. Routing of high speed signals, including The AD8114/AD8115 include 16 independent output buffers Video (NTSC, PAL, S, SECAM, YUV, RGB) that can be placed into a high impedance state for paralleling Compressed video (MPEG, wavelet) crosspoint outputs so that off channels do not load the output bus. 3-level digital video (HDB3) The AD8114 has a gain of 1, while the AD8115 offers a gain of 2. Data communications They operate on voltage supplies of 5 V while consuming only Telecommunications 70 mA of idle current. The channel switching is performed via a GENERAL DESCRIPTION serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control, allowing updating of an The AD8114/AD8115 are high speed, 16 16 video crosspoint individual output without reprogramming the entire array. switch matrices. They offer a 3 dB signal bandwidth greater than 200 MHz and channel switch times of less than 50 ns with 1% The AD8114/AD8115 is packaged in a 100-lead LQFP and is settling. With 70 dB of crosstalk and 98 dB isolation (at 5 MHz), available over the extended industrial temperature range of the AD8114/AD8115 are useful in many high speed applications. 40C to +85C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 19982016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ENABLE/DISABLE 01070-001AD8114/AD8115 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Input/Output Schematics .............................................................. 17 General Description ......................................................................... 1 Theory of Operation ...................................................................... 18 Functional Block Diagram .............................................................. 1 Applications ................................................................................ 18 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 19 Specifications ..................................................................................... 3 Gain Selection ............................................................................. 19 Timing Characteristics (Serial) .................................................. 5 Creating Larger Crosspoint Arrays .......................................... 19 Timing Characteristics (Parallel) ............................................... 6 Multichannel Video ................................................................... 21 Absolute Maximum Ratings ............................................................ 8 Crosstalk ...................................................................................... 21 Maximum Power Dissipation ..................................................... 8 Outline Dimensions ....................................................................... 24 ESD Caution .................................................................................. 8 Ordering Guide .......................................................................... 24 Pin Configuration and Function Descriptions ............................. 9 REVISION HISTORY 7/2016Rev. B to Rev. C 9/2005Rev. A to Rev. B Changes to General Description Section ...................................... 1 Updated Format .................................................................. Universal Changes to Off Isolation, Input-to-Output Parameter, Table 1 ........ 3 Change to Figure 3 ............................................................................ 6 Changes to Areas of Crosstalk Section ........................................ 22 Change to Absolute Maximum Ratings ......................................... 8 Deleted PCB Layout Section and Figure 50 Renumbered Changes to Maximum Power Dissipation Section ........................ 8 Sequentially ..................................................................................... 25 Updated Outline Dimensions ....................................................... 31 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 31 Changes to Ordering Guide .......................................................... 25 Deleted Figure 51 and Figure 52 ................................................... 26 11/2001Rev. 0 to Rev. A Deleted Figure 53 and Figure 54 ................................................... 27 Changes to Ordering Guide ............................................................. 5 Deleted Figure 55 and Figure 56 ................................................... 28 Updated Outline Dimensions ....................................................... 26 Deleted Evaluation Board Section and Figure 57 ....................... 29 10/1998Revision 0: Initial Version Deleted Control the Evaluation Board from a PC Section, Figure 58, Overshoot of PC Printer Ports Data Lines Section, and Figure 59 ................................................................................... 30 Rev. C Page 2 of 25