100 dB Range (10 nA to 1 mA) Logarithmic Converter Data Sheet AD8305 FEATURES FUNCTIONAL BLOCK DIAGRAM I V PD P Optimized for fiber optic photodiode interfacing 0.20 log 10 1nA VPOS Measures current over 5 decades VRDZ VOUT Law conformance 0.1 dB from 10 nA to 1 mA VREF 80k Single- or dual-supply operation (3 V to 12 V total) BIAS GENERATOR 2.5V Full log-ratio capabilities 200k 20k Nominal slope of 10 mV/dB (200 mV/decade) COMM 0.5V SCAL IREF Nominal intercept of 1 nA (set by external resistor) V BE2 14.2k BFIN V Optional adjustment of slope and intercept I BIAS LOG 451 Q2 TEMPERATURE + Complete and temperature stable COMPENSATION Q1 VLOG I PD Rapid response time for a given current level V BE1 6.69k INPT Miniature 16-lead chip scale package VSUM 0.5V COMM (LFCSP 3 mm 3 mm) VNEG COMM Low power: ~5 mA quiescent current Figure 1. APPLICATIONS Optical power measurement Wide range baseband logarithmic compression Measurement of current and voltage ratios Optical absorbance measurement GENERAL DESCRIPTION 1 The AD8305 is an inexpensive microminiature logarithmic converter The logarithmic intercept (also known as the reference current) is optimized for determining optical power in fiber optic systems. It uses nominally positioned at 1 nA by the use of the externally generated an advanced implementation of a classic translinear (junction based) current, I , of 10 A, provided by a 200 k resistor connected REF technique to provide a large dynamic range in a versatile and easily between VREF, at 2.5 V, and the reference input, IREF, at 0.5 V. The used form. A single-supply voltage of between 3 V and 12 V is intercept can be adjusted over a wide range by varying this resistor. adequate dual supplies may optionally be used. The low quiescent The AD8305 can also operate in a log ratio mode, with the numerator current (typically 5 mA) permits use in battery-operated applications. current applied to INPT and the denominator current applied to IREF. The input current, I , of 10 nA to 1 mA applied to the INPT pin is the PD A buffer amplifier is provided for driving a substantial load, for use in collector current of an optimally scaled NPN transistor, which converts raising the basic slope of 10 mV/dB to higher values, as a precision this current to a voltage (V ) with a precise logarithmic relationship. A BE comparator (threshold detector), or in implementing low-pass filters. second such converter is used to handle the reference current (IREF) Its rail-to-rail output stage can swing to within 100 mV of the positive applied to pin IREF. These input nodes are biased slightly above ground and negative supply rails, and its peak current sourcing capacity is (0.5 V). This is generally acceptable for photodiode applications where 25 mA. the anode does not need to be grounded. Similarly, this bias voltage is It is a fundamental aspect of translinear logarithmic converters that the easily accounted for in generating IREF. The output of the logarithmic small signal bandwidth falls as the current level diminishes, and the front end is available at Pin VLOG. low frequency noise-spectral density increases. At the 10 nA level, the The basic logarithmic slope at this output is nominally 200 mV/decade bandwidth of the AD8305 is about 50 kHz and increases in proportion (10 mV/dB). Thus, a 100 dB range corresponds to an output change of to I up to a maximum value of about 15 MHz. Using the buffer PD 1 V. When this voltage (or the buffer output) is applied to an ADC that amplifier, the increase in noise level at low currents can be addressed by permits an external reference voltage to be employed, the AD8305 using it to realize low-pass filters of up to three poles. voltage reference output of 2.5 V at Pin VREF can be used to improve The AD8305 is available in a 16-lead LFCSP package and is specified the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit), for operation from 40C to +85C. AD7823 (serial 8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of the logarithmic slope can be provided using a simple external resistor network. 1 Protected by U.S. Patent No. 5,519,308. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20022017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 03053-001AD8305 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Managing Intercept and Slope .................................................. 12 Applications ....................................................................................... 1 Response Time and Noise Considerations ............................. 12 Functional Block Diagram .............................................................. 1 Power Supply Sequencing ......................................................... 12 General Description ......................................................................... 1 Applications Information .............................................................. 14 Revision History ............................................................................... 2 Calibration ....................................................................................... 15 Specif icat ions ..................................................................................... 3 Using a Negative Supply ................................................................ 16 Absolute Maximum Ratings ............................................................ 4 Log-Ratio Applications .................................................................. 17 ESD Caution .................................................................................. 4 Reversing the Input Polarity ........................................................ 18 Pin Configuration and Function Descriptions ............................. 5 Characterization Methods ............................................................. 19 Typical Performance Characteristics ............................................. 6 Evaluation Board ............................................................................ 21 General Structure ........................................................................... 11 Outline Dimensions ....................................................................... 24 Theor y .......................................................................................... 11 Ordering Guide .......................................................................... 24 REVISION HISTORY 9/2017Rev. B to Rev. C Changed CP-16-2 to CP-16-27 .................................... Throughout Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 4/2010Rev. A to Rev. B Updated Data Sheet ............................................................ Universal Change to Figure 2 and Table 3 ...................................................... 5 Added Power Supply Sequencing Section ................................... 12 Added Figure 34 Renumbered Sequentially .............................. 12 Changes to Ordering Guide .......................................................... 24 3/2003Rev. 0 to Rev. A Changes to TPC 3 ............................................................................. 4 Changes to TPC 18 ........................................................................... 6 Changes to Figure 3 ........................................................................ 11 Changes to Figure 8 ........................................................................ 13 Updated Outline Dimensions ....................................................... 18 Rev. C Page 2 of 24