3.3 V, Upstream, Cable Line Driver Data Sheet AD8324 FEATURES FUNCTIONAL BLOCK DIAGRAM BYP Supports DOCSIS 2.0 and EuroDOCSIS specifications for reverse path transmission systems V V IN+ OUT+ Gain programmable in 1 dB steps over a 59 dB range DIFF ATTENUATION OUTPUT OR SINGLE VERNIER Low distortion at 61 dBmV output CORE STAGE INPUT 59 dBc SFDR at 21 MHz AMP V V IN OUT Z DIFF = 54 dBc SFDR at 65 MHz OUT Z (SINGLE) = 550 IN 8 75 Z (DIFF) = 1100 IN Output noise level at minimum gain 1.3 nV/Hz DECODE Maintains 75 output impedance in transmit-enable and POWER- RAMP 8 transmit-disable condition DOWN LOGIC AD8324 DATA LATCH Upper bandwidth of 100 MHz (full gain range) 3.3 V supply operation 8 SHIFT Supports SPI interfaces REGISTER APPLICATIONS GND DATEN SDATA CLK TXEN SLEEP DOCSIS 2.0 and EuroDOCSIS cable modems Figure 1. CATV set-top boxes CATV telephony modems Coaxial and twisted pair line drivers GENERAL DESCRIPTION 40 The AD8324 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8324 ideally suited for DOCSIS 2.0 and EuroDOCSIS applications. V = 61dBmV DEC 60 50 OUT The gain of the AD8324 is digitally controlled. An 8-bit serial THIRD HARMONIC word determines the desired output gain over a 59 dB range, resulting in gain changes of 1 dB/LSB. 60 The AD8324 accepts a differential or single-ended input signal. The output is specified for driving a 75 load through a 1:1 V = 61dBmV DEC 60 transformer. OUT 70 SECOND HARMONIC Distortion performance of 54 dBc is achieved with an output level up to 61 dBmV at 65 MHz bandwidth. 80 This device has a sleep mode function that reduces the quiescent 515 25 35 45 55 65 FREQUENCY (MHz) current to 30 A and a full power-down function that reduces Figure 2. Worst Harmonic Distortion vs. Frequency power-down current to 2.5 mA. The AD8324 is packaged in a low cost, 20-lead LFCSP and a 20-lead QSOP. The AD8324 operates from a single 3.3 V supply. Rev. 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DISTORTION (dBc) 04339-0-001 04339-0-002AD8324 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain Programming for the AD8324 ........................................ 12 Applications ....................................................................................... 1 Input Bias, Impedance, and Termination................................ 12 Functional Block Diagram .............................................................. 1 Output Bias, Impedance, and Termination ............................ 12 General Description ......................................................................... 1 Power Supply ............................................................................... 13 Revision History ............................................................................... 2 Signal Integrity Layout Considerations ................................... 13 Specifications ..................................................................................... 3 Initial Power-Up ......................................................................... 13 Logic Inputs (TTL-/CMOS-Compatible Logic) ....................... 4 RAMP Pin and BYP Pin Features ............................................ 13 Timing Requirements .................................................................. 5 Power Saving Features ............................................................... 14 Absolute Maximum Ratings ............................................................ 6 Distortion, Adjacent Channel Power, and DOCSIS .............. 14 Thermal Resistance ...................................................................... 6 Utilizing Diplex Filters ............................................................... 14 ESD Caution .................................................................................. 6 Noise and DOCSIS ..................................................................... 14 Pin Configuration and Function Descriptions ............................. 7 Differential Signal Source.......................................................... 15 Typical Performance Characteristics ............................................. 8 Differential Signal from Single-Ended Source ....................... 15 Test Circuit ...................................................................................... 11 Single-Ended Source .................................................................. 15 Applications Information .............................................................. 12 Outline Dimensions ....................................................................... 16 General Applications .................................................................. 12 Ordering Guide .......................................................................... 16 Circuit Description..................................................................... 12 REVISION HISTORY 5/16Rev. B to Rev. C Controlling Gain/Attenuation of the AD8324 Section, Change CP-20-1 to CP-20-6 .............................................. Universal Figure 28, Transmit Enable and Sleep Mode Section, and Changes to Figure 5, Figure 6, and Table 6 ................................... 7 Memory Functions Section ........................................................... 14 Changes to Figure 23 ...................................................................... 13 Changes to Distortion, Adjacent Channel Power, and DOCSIS Updated Outline Dimensions ....................................................... 16 Section and Noise and DOCSIS Section ..................................... 14 Changes to Ordering Guide .......................................................... 16 Deleted Figure 29 ............................................................................ 15 Changes to Differential Signal from Single-Ended Source 7/13Rev. A to Rev. B Section, Single-Ended Source Section, Figure 26, and Table 8 15 Updated Outline Dimensions ....................................................... 16 Changes to General Description Section ...................................... 1 Changes to Table 6 ............................................................................ 7 Changes to Ordering Guide .......................................................... 16 Added Test Circuits Section .......................................................... 11 Changed Applications Section to Applications Information 7/05Rev. 0 to Rev. A Section .............................................................................................. 12 Updated Absolute Maximum Ratings Page ................................... 5 Changes to Output Bias, Impedance, and Termination Section .... 12 Updated Outline Dimensions ....................................................... 16 Deleted Evaluation Board Features and Operation Section ..... 13 Changes to Ordering Guide .......................................................... 16 Deleted Overshoot on PC Printer Ports Section, Installing Visual Basic Control Software Section, Running AD8324 10/03Revision 0: Initial Version Software Section, Figure 27 Renumbered Sequentially, Rev. C Page 2 of 16