Ultralow Noise VGAs with Preamplifier and Programmable R IN Data Sheet AD8331/AD8332/AD8334 FEATURES FUNCTIONAL BLOCK DIAGRAM LON LOP VIP VIN VCM HILO Ultralow noise preamplifier (preamp) Voltage noise = 0.74 nV/Hz 3.5dB OR 15.5dB V MID LNA Current noise = 2.5 pA/Hz VOH 48dB 3 dB bandwidth 19dB 21dB PA INH ATTENUATOR + VOL AD8331: 120 MHz AD8332, AD8334: 100 MHz CLAMP LMD VCM GAIN Low power VGA BIAS AND BIAS CONTROL RCLMP INTERPOLATOR INTERFACE AD8331: 125 mW/channel AD8332, AD8334: 145 mW/channel AD8331/AD8332/AD8334 Wide gain range with programmable postamp ENB GAIN 4.5 dB to +43.5 dB in LO gain mode Figure 1. Signal Path Block Diagram 7.5 dB to 55.5 dB in HI gain mode 60 Low output-referred noise: 48 nV/Hz typical V = 1V GAIN HI GAIN MODE Active input impedance matching 50 V = 0.8V GAIN Optimized for 10-bit/12-bit ADCs Selectable output clamping level 40 V = 0.6V GAIN Single 5 V supply operation 30 AD8332 and AD8334 available in lead frame chip scale package V = 0.4V GAIN APPLICATIONS 20 V = 0.2V GAIN Ultrasound and sonar time-gain controls 10 V = 0V GAIN High performance automatic gain control (AGC) systems I/Q signal processing 0 High speed, dual ADC drivers 10 100k 1M 10M 100M 1G GENERAL DESCRIPTION FREQUENCY (Hz) The AD8331/AD8332/AD8334 are single-, dual-, and quad- Figure 2. Frequency Response vs. Gain channel, ultralow noise linear-in-dB, variable gain amplifiers Differential signal paths result in superb second- and third- (VGAs). Optimized for ultrasound systems, they are usable as a order distortion performance and low crosstalk. low noise variable gain element at frequencies up to 120 MHz. The low output-referred noise of the VGA is advantageous in Included in each channel are an ultralow noise preamp (LNA), driving high speed differential ADCs. The gain of the postamp an X-AMP VGA with 48 dB of gain range, and a selectable gain can be pin selected to 3.5 dB or 15.5 dB to optimize gain range postamp with adjustable output limiting. The LNA gain is 19 dB and output noise for 12-bit or 10-bit converter applications. The with a single-ended input and differential outputs. Using a single output can be limited to a user-selected clamping level, preventing resistor, the LNA input impedance can be adjusted to match a input overload to a subsequent ADC. An external resistor adjusts signal source without compromising noise performance. the clamping level. The 48 dB gain range of the VGA makes these devices suitable The operating temperature range is 40C to +85C. The for a variety of applications. Excellent bandwidth uniformity is AD8331 is available in a 20-lead QSOP package, the AD8332 is maintained across the entire range. The gain control interface available in 28-lead TSSOP and 32-lead LFCSP packages, and provides precise linear-in-dB scaling of 50 dB/V for control the AD8334 is available in a 64-lead LFCSP package. voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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GAIN (dB) 03199-002 03199-001AD8331/AD8332/AD8334 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Ultrasound TGC Application ................................................... 34 Applications ....................................................................................... 1 High Density Quad Layout ....................................................... 34 General Description ......................................................................... 1 AD8331 Evaluation Board ............................................................ 39 Functional Block Diagram .............................................................. 1 General Description ................................................................... 39 Revision History ............................................................................... 2 User-Supplied Optional Components ..................................... 39 Specifications ..................................................................................... 4 Measurement Setup.................................................................... 39 Absolute Maximum Ratings ............................................................ 7 Board Layout ............................................................................... 39 ESD Caution .................................................................................. 7 AD8331 Evaluation Board Schematics .................................... 40 Pin Configurations and Function Descriptions ........................... 8 AD8331 Evaluation Board PCB Layers ................................... 42 Typical Performance Characteristics ........................................... 12 AD8332 Evaluation Board ............................................................ 43 Test Circuits ..................................................................................... 20 General Description ................................................................... 43 Measurement Considerations ................................................... 20 User-Supplied Optional Components ..................................... 43 Theory of Operation ...................................................................... 24 Measurement Setup.................................................................... 43 Overview ...................................................................................... 24 Board Layout ............................................................................... 43 Low Noise Amplifier (LNA) ..................................................... 25 Evaluation Board Schematics ................................................... 44 Variable Gain Amplifier ............................................................ 27 AD8332 Evaluation Board PCB Layers ................................... 46 Postamplifier ............................................................................... 28 AD8334 Evaluation Board ............................................................ 47 Applications Information .............................................................. 30 General Description ................................................................... 47 LNAExternal Components .................................................... 30 Configuring the Input Impedance ........................................... 48 Driving ADCs ............................................................................. 32 Measurement Setup.................................................................... 48 Overload ...................................................................................... 32 Board Layout ............................................................................... 48 Optional Input Overload Protection ....................................... 32 Evaluation Board Schematics ................................................... 49 Layout, Grounding, and Bypassing .......................................... 33 AD8334 Evaluation Board PCB Layers ................................... 51 Multiple Input Matching ........................................................... 33 Outline Dimensions ....................................................................... 53 Disabling the LNA ...................................................................... 33 Ordering Guide .......................................................................... 55 REVISION HISTORY 5/2016Rev. H to Rev. I Changes to Figure 6 and Table 6 ................................................... 10 Changes to Figure 5, and Table 5 .................................................... 9 Changes to Figure 33 ...................................................................... 16 Updated Outline Dimensions ....................................................... 54 Changes to Figure 64 ...................................................................... 22 Changes to Ordering Guide .......................................................... 55 Changes to Figure 70 ...................................................................... 24 Changes to Low Noise Amplifier (LNA) Section and 3/2015Rev. G to Rev. H Figure 74 .......................................................................................... 25 Changes to Pin 29 Description Table 6 ....................................... 11 Changes to Figure 94 ...................................................................... 38 Updated Figure 123, Figure 124, Figure 125 Outline Changes to General Descriptions Section, Figure 95 Caption, Table 10, and Board Layout Section ............................................. 39 Dimensions ...................................................................................... 53 Changes to Ordering Guide .......................................................... 55 Changes to Figure 96 ...................................................................... 40 Changes to Figure 97 ...................................................................... 41 10/2010Rev. F to Rev. G Changes to Figure 98 and Figure 103 .......................................... 42 Changes to Quiescent Current per Channel Parameter, Deleted AD8331 Bill of Materials Section and Table 11 Table 1 ................................................................................................ 6 Renumbered Sequentially ............................................................. 43 Changes to Pin 1, Table 3 ................................................................. 8 Changes to Figure 104 ................................................................... 43 Changes to Pin 1 and Pin 28, Table 4 and Pin 4 and Pin 5, Changes to Figure 106 ................................................................... 45 Table 5 ................................................................................................ 9 Changes to Figure 107 ................................................................... 46 Rev. I Page 2 of 55