45 dB Digitally Controlled VGA LF to 600 MHz AD8369 FEATURES FUNCTIONAL BLOCK DIAGRAM Digitally Controlled Variable Gain in 3 dB Steps BIT3 BIT2 BIT1 BIT0 5 dB to +40 dB (R = 1 k ) L 10 dB to +35 dB (R = 200 ) L VPOS Less than 0.2 dB Flatness over a +20 MHz Bandwidth BIAS 3dB STEP DENB PWUP GAIN CODE DECODE up to 380 MHz SENB 4-Bit Parallel or 3-Wire Serial Interface FILT Differential 200 Input and Output Impedance OPHI Single 3.0 V5.5 V Supply Gm CELLS OPLO Draws 37 mA at 5 V Power-Down <1 mA Maximum APPLICATIONS INHI Cellular/PCS Base Stations IF Sampling Receivers CMDC Fixed Wireless Access INLO Wireline Modems COMM Instrumentation COMM PRODUCT DESCRIPTION OPHI and OPLO. The overall gain depends upon the source The AD8369 is a high performance digitally controlled variable and load impedances due to the resistive nature of the input and gain amplifier (VGA) for use from low frequencies to a 3 dB output ports. frequency of 600 MHz at all gain codes. The AD8369 delivers Digital control of the AD8369 is achieved using either a serial or excellent distortion performance: the two-tone, third-order a parallel interface. The mode of digital control is selected by intermodulation distortion is 69 dBc at 70 MHz for a 1 V p-p connecting a single pin (SENB) to ground or the positive sup- composite output into a 1 kW load. The AD8369 has a nominal ply. Digital control pins can be driven with standard CMOS noise figure of 7 dB when at maximum gain, then increases with logic levels. decreasing gain. Output IP3 is +19.5 dBm at 70 MHz into a The AD8369 may be powered on or off by a logic level applied 1 kW load and remains fairly constant over the gain range. to the PWUP pin. For a logic high, the chip powers up rapidly The signal input is applied to pins INHI and INLO. Variable gain to its nominal quiescent current of 37 mA at 25C. When low, is achieved via two methods. The 6d B gain steps are implemented the total dissipation drops to less than a few milliwatts. using a discrete X-AMP structure, in which the input signal is The AD8369 is fabricated on an Analog Devices proprietary, high progressively attenuated by a 200 W R-2R ladder network that performance 25 GHz silicon bipolar IC process and is available also sets the input impedance the 3 dB steps are implemented at in a 16-lead TSSOP package for the industrial temperature range the output of the amplifier. This combination provides very of 40 rC to +85 r C. A populated evaluation board is available. accurate 3 dB gain steps over a span of 45 dB. The output imped- ance is set by on-chip resistors across the differential output pins, Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com (V = 5 V, T = 25 C, R = 200 , R = 1000 , Frequency = 70 MHz, at maximum gain, S S L AD8369SPECIFICATIONS unless otherwise noted.) Parameter Conditions Min Typ Max Unit OVERALL FUNCTION Frequency Range 3 dB Bandwidth LF* 600 MHz GAIN CONTROL INTERFACE Voltage Gain Span 45 dB Maximum Gain All bits high (1 1 1 1) 40 dB Minimum Gain All bits low (0 0 0 0) 5 dB Gain Step Size 3dB Gain Step Accuracy Over entire gain range, with respect to 3 dB step 0.05 dB Gain Step Response Time Step = 3 dB, settling to 10% of final value 30 ns INPUT STAGE Input Resistance From INHI to INLO 200 W From INHI to COMM, from INLO to COMM 100 W Input Capacitance From INHI to INLO 0.1 pF From INHI to COMM, from INLO to COMM 1.1 pF Input Noise Spectral Density 2 nV/Hz Input Common-Mode DC Voltage Measured at pin CMDC 1.7 V Maximum Linear Input V V at Minimum Gain 2.2 V INHI INLO OUTPUT STAGE Output Resistance From OPHI to OPLO 200 W From OPHI to COMM, from OPLO to COMM 100 W Output Capacitance From OPHI to OPLO 0.25 pF From OPHI to COMM, from OPLO to COMM 1.5 pF Common-Mode DC Voltage No input signal V /2 V S Slew Rate Output step = 1 V 1200 V/ms POWER INTERFACE Supply Voltage 3.0 5.5 V Quiescent Current PWUP high 37 42 mA vs. Temperature 40 r C T 85rC52mA A Disable Current PWUP low 400 750 mA vs. Temperature 40 r C T 85rC1mA A POWER UP INTERFACE Pin PWUP Enable Threshold 1.0 V Disable Threshold 2.2 V Response Time Time delay following low to high transition 7 ms on PWUP until output settles to within 10% of final value Input Bias Current PWUP = 5 V 160 mA DIGITAL INTERFACE Pins SENB, BIT0, BIT1, BIT2, BIT3, and DENB Low Condition 2.0 V High Condition 3.0 V Input Bias Current Low input 150 mA Frequency = 10 MHz Voltage Gain 40.5 dB Gain Flatness Within 10 MHz of 10 MHz +0.05* dB Noise Figure 7.0 dB Output IP3 f1 = 9.945 MHz, f2 = 10.550 MHz +22 dBV rms +22 dBm IMD f1 = 9.945 MHz, f2 = 10.550 MHz 3 V V = 1 V p-p composite 74 dBc OPHI OPLO Harmonic Distortion Second-Order, V V = 1 V p-p 72 dBc OPHI OPLO Third-Order, V V = 1 V p-p 71 dBc OPHI OPLO P1dB For 1 dB deviation from linear gain +3 dBV rms +3 dBm *The low frequency high-pass corner is determined by the capacitor on pin FILT, C . See the Theory of Operation section for details. FILT 2 REV. A