Ultralow Distortion IF VGA Data Sheet AD8375 FEATURES FUNCTIONAL BLOCK DIAGRAM VPOS COMM Bandwidth of 630 MHz (3 dB) Gain range: 4 dB to +20 dB VCOM PWUP Step size: 1 dB 0.2 dB AD8375 OUT+ Differential input and output Noise figure: 8 dB maximum gain VIN+ OUT+ Output IP3 of ~50 dBm at 200 MHz POST-AMP Output P1dB of 19 dBm at 200 MHz OUT VIN Provides constant SFDR vs. gain OUT Parallel 5-bit control interface REGISTERS Power-down feature AND GAIN DECODER Single 5 V supply operation 24-lead, 4 mm 4 mm LFCSP APPLICATIONS A4 A3 A2 A1 A0 Figure 1. Differential ADC drivers High IF sampling receivers Wideband multichannel receivers Instrumentation GENERAL DESCRIPTION The AD8375 is a digitally controlled, variable gain, wide Fabricated on an Analog Devices, Inc., high speed SiGe process, bandwidth amplifier that provides precise gain control, high the AD8375 is supplied in a compact, thermally enhanced, IP3, and low noise figure. The excellent distortion performance 4 mm 4 mm, 24-lead LFCSP package and operates over the and high signal bandwidth make the AD8375 an excellent gain temperature range of 40C to +85C. control device for a variety of receiver applications. 40 65 Using an advanced high speed SiGe process and incorporating 50 60 proprietary distortion cancellation techniques, the AD8375 achieves 50 dBm output IP3 at 200 MHz. 60 55 OIP3 The AD8375 provides a broad 24 dB gain range with 1 dB 70 50 resolution. The gain is adjusted through a 5-pin control interface and can be driven using standard TTL levels. The open-collector 80 45 outputs provide a flexible interface, allowing the overall signal HD2 90 40 gain to be set by the loading impedance. Thus, the signal voltage gain is directly proportional to the load. HD3 100 35 The AD8375 is powered on by applying the appropriate logic 110 30 level to the PWUP pin. The quiescent current of the AD8375 is 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) typically 130 mA. When powered down, the AD8375 consumes less than 5 mA and offers excellent input-to-output isolation. Figure 2. Harmonic Distortion and Output IP3 vs. Frequency Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com HARMONIC DISTORTION (dBc), OUTPUT 2V p-p OIP3 (dBm), OUTPUT 3dBm/TONE 06724-001 06724-052AD8375 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Structure ............................................................................ 12 Applications ....................................................................................... 1 Applications ..................................................................................... 13 Functional Block Diagram .............................................................. 1 Basic Connections ...................................................................... 13 General Description ......................................................................... 1 Single-Ended-to-Differential Conversion ............................... 13 Revision History ............................................................................... 2 Broadband Operation ................................................................ 14 Specifications ..................................................................................... 3 ADC Interfacing ......................................................................... 14 Absolute Maximum Ratings ............................................................ 5 Layout Considerations ............................................................... 17 ESD Caution .................................................................................. 5 Characterization Test Circuits .................................................. 17 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ........................................................................ 18 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 22 Circuit Description ......................................................................... 12 Ordering Guide .......................................................................... 22 REVISION HISTORY 8/2017Rev. A to Rev. B Changed CP-24-1 to CP-24-10 .................................... Throughout Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 10/2012Rev. 0 to Rev. A Change to Maximum Junction Temperature Parameter, Table 3 ................................................................................................ 5 Added Exposed Pad Notation, Figure 3 and Exposed Pad Notation, Table 4 ............................................................................... 6 Added Exposed Pad Notation to Outline Dimensions ............. 22 8/2007Revision 0: Initial Version Rev. B Page 2 of 24