Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC Data Sheet AD9239 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND 4 ADCs in 1 package Coded serial digital outputs with ECC per channel AD9239 On-chip temperature sensor VIN + A DOUT + A PIPELINE 95 dB channel-to-channel crosstalk BUF SHA 12 CHANNEL A ADC VIN A DOUT A SNR = 65 dBFS with AIN = 85 MHz at 250 MSPS VCM A SFDR = 77 dBc with AIN = 85 MHz at 250 MSPS VIN + B DOUT + B PIPELINE SHA 12 CHANNEL B BUF Excellent linearity ADC VIN B DOUT B DNL = 0.3 LSB (typical) VCM B INL = 0.7 LSB (typical) VIN + C DOUT + C PIPELINE SHA CHANNEL C BUF 12 ADC 780 MHz full power analog bandwidth VIN C DOUT C VCM C Power dissipation = 380 mW per channel at 250 MSPS VIN + D DOUT + D 1.25 V p-p input voltage range, adjustable up to 1.5 V p-p PIPELINE BUF SHA 12 CHANNEL D ADC VIN D DOUT D 1.8 V supply operation VCM D Clock duty cycle stabilizer PGM3 REFERENCE Serial port interface features PGM2 RBIAS DATA RATE Power-down modes PGM1 MULTIPLIER Digital test pattern enable SERIAL TEMPOUT PGM0 PORT Programmable header RESET Programmable pin functions (PGMx, PDWN) SCLK SDI/ SDO CSB CLK+ CLK SDIO APPLICATIONS Figure 1. Communication receivers Cable head end equipment/M-CMTS Broadband radios Wireless infrastructure transceivers Radar/military-aerospace subsystems Test equipment GENERAL DESCRIPTION The AD9239 is a quad, 12-bit, 250 MSPS analog-to-digital Fabricated on an advanced CMOS process, the AD9239 is avail- converter (ADC) with an on-chip temperature sensor and a able in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is high speed serial interface. It is designed to support digitizing specified over the industrial temperature range of 40C to +85C. high frequency, wide dynamic range signals with an input PRODUCT HIGHLIGHTS bandwidth up to 780 MHz. The output data are serialized and 1. Four ADCs are contained in a small, space-saving package. presented in packet format, consisting of channel-specific 2. An on-chip PLL allows users to provide a single ADC information, coded samples, and error correction code. sampling clock, and the PLL distributes and multiplies up The ADC requires a single 1.8 V power supply and the input to produce the corresponding data rate clock. clock may be driven differentially with a sine wave, LVPECL, 3. Coded data rate supports up to 4.0 Gbps per channel. TTL, or LVDS. A clock duty cycle stabilizer allows high Coding includes scrambling to ensure proper dc common performance at full speed with a wide range of clock duty mode, embedded clock, and error correction. cycles. The on-chip reference eliminates the need for external 4. The AD9239 operates from a single 1.8 V power supply. decoupling and can be adjusted by means of SPI control. 5. Flexible synchronization schemes and programmable Various power-down and standby modes are supported. The mode pins. ADC typically consumes 145 mW per channel with the digital 6. On-chip temperature sensor. link still in operation when standby operation is enabled. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com DATA SERIALIZER, ENCODER, AND CML DRIVERS 06980-001AD9239 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Equivalent Circuits ......................................................................... 17 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 19 General Description ......................................................................... 1 Analog Input Considerations ................................................... 19 Product Highlights ........................................................................... 1 Clock Input Considerations ...................................................... 21 Revision History ............................................................................... 2 Serial Port Interface (SPI) .............................................................. 31 Specifications ..................................................................................... 3 Hardware Interface ..................................................................... 31 AC Specifications .......................................................................... 4 Memory Map .................................................................................. 33 Digital Specifications ................................................................... 5 Reading the Memory Map Table .............................................. 33 Switching Specifications .............................................................. 6 Reserved Locations .................................................................... 33 Timing Diagram ........................................................................... 7 Default Values ............................................................................. 33 Absolute Maximum Ratings ............................................................ 8 Logic Levels ................................................................................. 33 Thermal Resistance ...................................................................... 8 Outline Dimensions ....................................................................... 38 ESD Caution .................................................................................. 8 Ordering Guide .......................................................................... 38 Pin Configuration and Function Description .............................. 9 REVISION HISTORY 7/14Rev. D to Rev. E 5/10Rev. A to Rev. B Changes to Digital Start-Up Sequence Section .......................... 23 Changes to Table 15 ................................................................. 35, 36 Added Minimize Skew and Time Misalignment (Optional) Section, Link Initialization (Required) Section, and Table 9 2/10Rev. 0 to Rev. A Renumbered Sequentially .............................................................. 23 Changes to Analog Inputs, Differential Input Voltage Range Changes to Table 16 ........................................................................ 34 Parameter and Endnote 3, Table 1 .................................................. 3 Changes to Table 8 ............................................................................. 9 5/14Rev. C to Rev. D Changes to Clock Duty Cycle Considerations Section ............. 21 Changes to Digital Outputs and Timing Section ....................... 25 Changes to Digital Outputs and Timing Section ....................... 23 Changes to Table 15 ....................................................................... 34 Changes to Table 15 ........................................................................ 35 6/13Rev. B to Rev. C 10/08Revision 0: Initial Version Changed Temperature Sensor Output Current Drive from 10 A to 50 A Table 1 .................................................................... 3 Changes to Digital Outputs and Timing Section ....................... 24 Updated Outline Dimensions ....................................................... 38 Rev. E Page 2 of 40